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/Documentation/devicetree/bindings/input/
Dpwm-vibrator.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/input/pwm-vibrator.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Sebastian Reichel <sre@kernel.org>
14 strength increases based on the duty cycle of the enable PWM channel
15 (100% duty cycle meaning strongest vibration, 0% meaning no vibration).
18 driven at fixed duty cycle. If available this is can be used to increase
23 const: pwm-vibrator
25 pwm-names:
[all …]
/Documentation/devicetree/bindings/regulator/
Dpwm-regulator.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/regulator/pwm-regulator.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Brian Norris <briannorris@chromium.org>
11 - Lee Jones <lee@kernel.org>
12 - Alexandre Courbot <acourbot@nvidia.com>
19 duty-cycle values must be provided via DT. Limitations are that the
21 Intermediary duty-cycle values which would normally allow finer grained
23 is given to the user if the assumptions made in continuous-voltage mode do
[all …]
/Documentation/hwmon/
Ddme1737.rst18 Addresses scanned: none, address read from Super-I/O config space
34 Addresses scanned: none, address read from Super-I/O config space
43 -----------------
52 Include non-standard LPC addresses 0x162e and 0x164e
55 - VIA EPIA SN18000
59 -----------
63 and SCH5127 Super-I/O chips. These chips feature monitoring of 3 temp sensors
64 temp[1-3] (2 remote diodes and 1 internal), 8 voltages in[0-7] (7 external and
65 1 internal) and up to 6 fan speeds fan[1-6]. Additionally, the chips implement
66 up to 5 PWM outputs pwm[1-3,5-6] for controlling fan speeds both manually and
[all …]
Dvt1211.rst10 Addresses scanned: none, address read from Super-I/O config space
24 -----------------
29 configuration for channels 1-5.
30 Legal values are in the range of 0-31. Bit 0 maps to
47 -----------
49 The VIA VT1211 Super-I/O chip includes complete hardware monitoring
52 implements 5 universal input channels (UCH1-5) that can be individually
60 connected to the PWM outputs of the VT1211 :-().
80 ------------------
82 Voltages are sampled by an 8-bit ADC with a LSB of ~10mV. The supported input
[all …]
Dlm93.rst10 Addresses scanned: I2C 0x2c-0x2e
18 Addresses scanned: I2C 0x2c-0x2e
24 - Mark M. Hoffman <mhoffman@lightlink.com>
25 - Ported to 2.6 by Eric J. Bowersox <ericb@aspsys.com>
26 - Adapted to 2.6.20 by Carsten Emde <ce@osadl.org>
27 - Modified for mainline integration by Hans J. Koch <hjk@hansjkoch.de>
30 -----------------
33 Set to non-zero to force some initializations (default is 0).
38 Configures in7 and in8 limit type, where 0 means absolute and non-zero
54 --------------------
[all …]
Dmax31790.rst10 Addresses scanned: -
18 -----------
23 PWM outputs. The desired fan speeds (or PWM duty cycles) are written
24 through the I2C interface. The outputs drive "4-wire" fans directly,
28 Tachometer inputs monitor fan tachometer logic outputs for precise (+/-1%)
35 -------------
38 fan[1-12]_input RO fan tachometer speed in RPM
39 fan[1-12]_fault RO fan experienced fault
40 fan[1-6]_target RW desired fan speed in RPM
41 fan[1-6]_enable RW enable or disable the tachometer input
[all …]
Df71882fg.rst103 This is the 64-pin variant of the F71889FG, they have the
119 -----------
133 ----------
136 interface as documented in sysfs-interface, without any exceptions.
140 -----------
142 Both PWM (pulse-width modulation) and DC fan speed control methods are
149 vica versa. So the temperature zone trip points 1-4 (or 1-2) go from high temp
153 There are 2 modes to specify the speed of the fan, PWM duty cycle (or DC
154 voltage) mode, where 0-100% duty cycle (0-100% of 12V) is specified. And RPM
156 gets specified as 0-100% of the fan#_full_speed file.
[all …]
Dw83792d.rst10 Addresses scanned: I2C 0x2c - 0x2f
19 -----------------
35 -----------
42 parameter; this will put it into a more well-behaved state first.
48 The driver also implements up to seven fan control outputs: pwm1-7. Pwm1-7
53 Automatic fan control mode is possible only for fan1-fan3.
116 ----------------
118 - This driver is only for Winbond W83792D C version device, there
120 calculation method to in6-in7(measured value, limits) is a little
123 - The function of vid and vrm has not been finished, because I'm NOT
[all …]
Dmax6639.rst12 Datasheet: https://datasheets.maximintegrated.com/en/ds/MAX6639-MAX6639F.pdf
15 - He Changqing <hechangqing@semptian.com>
16 - Roland Stigge <stigge@antcom.de>
19 -----------
21 This driver implements support for the Maxim MAX6639. This chip is a 2-channel
23 temperature and one external diode-connected transistor or two external
24 diode-connected transistors.
43 pwm1 RW Fan 1 target duty cycle (0..255)
44 pwm2 RW Fan 2 target duty cycle (0..255)
Dnzxt-smart2.rst1 .. SPDX-License-Identifier: GPL-2.0-or-later
3 Kernel driver nzxt-smart2
8 - NZXT RGB & Fan controller
9 - NZXT Smart Device v2
12 -----------
15 Besides typical speed monitoring and PWM duty cycle control, voltage and current
25 -----------
43 -------------
46 fan[1-3]_input Fan speed monitoring (in rpm).
47 curr[1-3]_input Current supplied to the fan (in milliamperes).
[all …]
Dmax16601.rst1 .. SPDX-License-Identifier: GPL-2.0
12 Addresses scanned: -
20 Addresses scanned: -
28 Addresses scanned: -
36 Addresses scanned: -
40 Author: Guenter Roeck <linux@roeck-us.net>
44 -----------
46 This driver supports the MAX16508 VR13 Dual-Output Voltage Regulator
47 as well as the MAX16600, MAX16601, and MAX16602 VR13.HC Dual-Output
55 -----------
[all …]
/Documentation/driver-api/thermal/
Dcpu-idle-cooling.rst1 .. SPDX-License-Identifier: GPL-2.0
8 ----------
26 budget lower than the requested one and under-utilize the CPU, thus
27 losing performance. In other words, one OPP under-utilizes the CPU
33 ----------
37 decrease. Acting on the idle state duration or the idle cycle
47 At a specific OPP, we can assume that injecting idle cycle on all CPUs
58 ---------------
61 idle state for a specified time each control cycle, it provides
71 or decreased by modulating the duty cycle of the idle injection.
[all …]
/Documentation/userspace-api/media/rc/
Dlirc-set-send-duty-cycle.rst1 .. SPDX-License-Identifier: GPL-2.0 OR GFDL-1.1-no-invariants-or-later
13 LIRC_SET_SEND_DUTY_CYCLE - Set the duty cycle of the carrier signal for
30 Duty cicle, describing the pulse width in percent (from 1 to 99) of
31 the total cycle. Values 0 and 100 are reserved.
36 Get/set the duty cycle of the carrier signal for IR transmit.
45 On success 0 is returned, on error -1 and the ``errno`` variable is set
47 :ref:`Generic Error Codes <gen-errors>` chapter.
Dlirc-func.rst1 .. SPDX-License-Identifier: GPL-2.0 OR GFDL-1.1-no-invariants-or-later
12 lirc-read
13 lirc-write
14 lirc-get-features
15 lirc-get-send-mode
16 lirc-get-rec-mode
17 lirc-get-rec-resolution
18 lirc-set-send-duty-cycle
19 lirc-get-timeout
20 lirc-set-rec-timeout
[all …]
Dlirc-get-features.rst1 .. SPDX-License-Identifier: GPL-2.0 OR GFDL-1.1-no-invariants-or-later
13 LIRC_GET_FEATURES - Get the underlying hardware device's features
41 .. _LIRC-CAN-REC-RAW:
47 .. _LIRC-CAN-REC-PULSE:
52 :ref:`LIRC_MODE_PULSE <lirc-mode-pulse>` can only be used for transmitting.
54 .. _LIRC-CAN-REC-MODE2:
59 :ref:`LIRC_MODE_MODE2 <lirc-mode-MODE2>` is used. This also implies
60 that :ref:`LIRC_MODE_SCANCODE <lirc-mode-SCANCODE>` is also supported,
64 .. _LIRC-CAN-REC-LIRCCODE:
70 .. _LIRC-CAN-REC-SCANCODE:
[all …]
/Documentation/devicetree/bindings/leds/irled/
Dir-spi-led.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/leds/irled/ir-spi-led.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Sean Young <sean@mess.org>
17 - $ref: /schemas/spi/spi-peripheral-props.yaml#
21 const: ir-spi-led
26 duty-cycle:
32 led-active-low:
37 power-supply: true
[all …]
/Documentation/devicetree/bindings/hwmon/
Dadt7475.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jean Delvare <jdelvare@suse.com>
23 https://www.onsemi.com/pub/Collateral/ADT7473-D.PDF
24 https://www.onsemi.com/pub/Collateral/ADT7475-D.PDF
25 https://www.onsemi.com/pub/Collateral/ADT7476-D.PDF
26 https://www.onsemi.com/pub/Collateral/ADT7490-D.PDF
34 - adi,adt7473
35 - adi,adt7475
[all …]
/Documentation/devicetree/bindings/pwm/
Dmicrochip,corepwm.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Conor Dooley <conor.dooley@microchip.com>
16 https://www.microsemi.com/existing-parts/parts/152118
19 - $ref: pwm.yaml#
24 - const: microchip,corepwm-rtl-v4
32 "#pwm-cells":
37 microchip,sync-update-mask:
45 control the duty cycle for channel x have a second "shadow"/buffer reg synthesised.
[all …]
Dclk-pwm.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/pwm/clk-pwm.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Nikita Travkin <nikita@trvn.ru>
15 It's often possible to control duty-cycle of such clocks which makes them
19 - $ref: pwm.yaml#
23 const: clk-pwm
29 "#pwm-cells":
35 - compatible
[all …]
/Documentation/ABI/testing/
Dsysfs-class-pwm6 The pwm/ class sub-directory belongs to the Generic PWM
32 Value is between 0 and /sys/class/pwm/pwmchipN/npwm - 1.
62 Sets the PWM signal duty cycle in nanoseconds.
87 pair unsigned integers (period and duty cycle), separated by a
/Documentation/leds/
Dleds-mlxcpld.rst10 -----------
14 - mlxcpld:fan1:green
15 - mlxcpld:fan1:red
16 - mlxcpld:fan2:green
17 - mlxcpld:fan2:red
18 - mlxcpld:fan3:green
19 - mlxcpld:fan3:red
20 - mlxcpld:fan4:green
21 - mlxcpld:fan4:red
22 - mlxcpld:psu:green
[all …]
Dleds-lp3944.rst5 * National Semiconductor LP3944 Fun-light Chip
21 -----------
29 - period:
31 - duty cycle:
42 -----
47 according to include/linux/leds-lp3944.h, set the i2c board info::
/Documentation/devicetree/bindings/media/
Damlogic,meson-ir-tx.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/media/amlogic,meson-ir-tx.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Viktor Prutyanov <viktor.prutyanov@phystech.edu>
16 sending IR signals with arbitrary carrier frequency and duty cycle.
21 - const: amlogic,meson-ir-tx
22 - items:
23 - const: amlogic,meson-g12a-ir-tx
24 - const: amlogic,meson-ir-tx
[all …]
/Documentation/driver-api/
Dmiscellaneous.rst4 .. kernel-doc:: include/linux/parport.h
7 .. kernel-doc:: drivers/parport/ieee1284.c
10 .. kernel-doc:: drivers/parport/share.c
13 .. kernel-doc:: drivers/parport/daisy.c
19 .. kernel-doc:: drivers/tty/serial/8250/8250_core.c
24 Pulse-Width Modulation (PWM)
27 Pulse-width modulation is a modulation technique primarily used to
33 are expected to embed this structure in a driver-specific structure.
38 performed on PWM devices to control the period, duty cycle, polarity and
44 .. kernel-doc:: include/linux/pwm.h
[all …]
/Documentation/devicetree/bindings/pinctrl/
Drealtek,rtd1315e-pinctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/pinctrl/realtek,rtd1315e-pinctrl.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - TY Chang <tychang@realtek.com>
14 The Realtek DHC RTD1315E is a high-definition media processor SoC. The
20 const: realtek,rtd1315e-pinctrl
26 '-pins$':
29 - $ref: pincfg-node.yaml#
30 - $ref: pinmux-node.yaml#
[all …]

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