Searched full:dvfs (Results 1 – 25 of 29) sorted by relevance
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| /Documentation/devicetree/bindings/regulator/ |
| D | tps51632-regulator.txt | 8 - ti,enable-pwm-dvfs: Enable the DVFS voltage control through the PWM interface.
9 - ti,dvfs-step-20mV: The 20mV step voltage when PWM DVFS enabled. Missing this
10 will set 10mV step voltage in PWM DVFS mode. In normal mode, the voltage
25 ti,enable-pwm-dvfs;
26 ti,dvfs-step-20mV;
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| /Documentation/scheduler/ |
| D | schedutil.rst | 51 Dynamic Voltage and Frequency Scaling (DVFS) ratio and one microarch ratio.
53 For simple DVFS architectures (where software is in full control) we trivially
60 For more dynamic systems where the hardware is in control of DVFS we use
84 of DVFS and CPU type. IOW. we can transfer and compare them between CPUs.
98 (DVFS) ramp-up after they are running again.
120 Schedutil / DVFS
125 DVFS state.
150 Because these callbacks are directly from the scheduler, the DVFS hardware
152 rate-limiting DVFS requests for when hardware interaction is slow and
161 - On low-load scenarios, where DVFS is most relevant, the 'running' numbers
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| /Documentation/devicetree/bindings/mfd/ |
| D | rohm,bd9571mwv.yaml | 68 "^(vd09|vd18|vd25|vd33|dvfs)$":
74 pattern: "^(vd09|vd18|vd25|vd33|dvfs)$"
118 dvfs: dvfs {
119 regulator-name = "dvfs";
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| D | mediatek,mt8195-scpsys.yaml | 15 domain control, thermal measurement, DVFS, etc.
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| /Documentation/translations/zh_CN/scheduler/ |
| D | schedutil.rst | 53 Frequency Scaling，DVFS）比率，另一个是微架构比率。
96 因此它们在再次运行后会面临（DVFS）的上涨。
119 Schedutil / DVFS
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| D | sched-capacity.rst | 33 - 在动态电压频率升降（Dynamic Voltage and Frequency Scaling，DVFS）框架中，不是所有的CPU都
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| /Documentation/devicetree/bindings/clock/ |
| D | imx31-clock.yaml | 88 interrupt for DVFS when a frequency change is requested, request 2 is
91 - description: CCM DVFS interrupt request 1
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| /Documentation/translations/zh_CN/ |
| D | glossary.rst | 17 * DVFS: 动态电压频率升降。（Dynamic Voltage and Frequency Scaling）
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| /Documentation/devicetree/bindings/firmware/ |
| D | arm,scpi.yaml | 123 "arm,scpi-dvfs-clocks" - all the clocks that are variable and index
137 - arm,scpi-dvfs-clocks
190 compatible = "arm,scpi-dvfs-clocks";
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| /Documentation/driver-api/thermal/ |
| D | cpu-cooling-api.rst | 76 - The voltage and frequency levels as a result of DVFS. The DVFS
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| D | intel_dptf.rst | 254 DVFS attributes
256 :file:`/sys/bus/pci/devices/0000\:00\:04.0/dvfs/`
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| /Documentation/devicetree/bindings/cpufreq/ |
| D | qemu,virtual-cpufreq.yaml | 28 contiguously and contain registers for controlling DVFS(Dynamic Frequency
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| D | brcm,stb-avs-cpu-freq.txt | 16 firmware. On some SoCs, this firmware supports DFS and DVFS in addition to
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| D | apple,cluster-cpufreq.yaml | 13 Apple SoCs (e.g. M1) have a per-cpu-cluster DVFS controller that is part of
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| D | cpufreq-st.txt | 31 Dynamic Voltage and Frequency Scaling (DVFS)
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| /Documentation/devicetree/bindings/thermal/ |
| D | nvidia,tegra30-tsensor.yaml | 19 Generates an interrupt to SW to lower temperature via DVFS on reaching
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| D | thermal-cooling-devices.yaml | 30 scaling (DVFS), and uses lower frequencies as cooling states.
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| /Documentation/devicetree/bindings/opp/ |
| D | opp-v2.yaml | 24 * Example 1: Single cluster Dual-core ARM cortex A9, switch DVFS states
81 * Example 2: Single cluster, Quad-core Qualcom-krait, switches DVFS states
137 * Missing opp-shared property means CPUs switch DVFS states
166 * DVFS state together.
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| D | opp-v2-base.yaml | 30 their DVFS state together, i.e. they share clock/voltage/current lines.
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| /Documentation/devicetree/bindings/soc/mediatek/ |
| D | mtk-svs.yaml | 18 chip process corner, temperatures and other factors. Then DVFS
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| D | scpsys.txt | 6 voltage frequency scaling (DVFS), interrupt filter and lowlevel sleep control.
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| /Documentation/devicetree/bindings/dvfs/ |
| D | performance-domain.yaml | 4 $id: http://devicetree.org/schemas/dvfs/performance-domain.yaml#
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| /Documentation/devicetree/bindings/power/ |
| D | fsl,imx-gpc.yaml | 13 The i.MX6 General Power Control (GPC) block contains DVFS load tracking
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| /Documentation/cpu-freq/ |
| D | cpu-drivers.rst | 129 | | (online + offline) CPUs that do DVFS |
250 particular order, but if they are cpufreq core will do DVFS a bit
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| /Documentation/devicetree/bindings/memory-controllers/ |
| D | rockchip,rk3399-dmc.yaml | 44 The CPU interrupt number. It should be a DCF interrupt. When DDR DVFS
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