| /Documentation/devicetree/bindings/edac/ |
| D | socfpga-eccmgr.txt | 1 Altera SoCFPGA ECC Manager
2 This driver uses the EDAC framework to implement the SOCFPGA ECC Manager.
3 The ECC Manager counts and corrects single bit errors and counts/handles
6 Cyclone5 and Arria5 ECC Manager
8 - compatible : Should be "altr,socfpga-ecc-manager"
15 L2 Cache ECC
17 - compatible : Should be "altr,socfpga-l2-ecc"
18 - reg : Address and size for ECC error interrupt clear registers.
22 On Chip RAM ECC
24 - compatible : Should be "altr,socfpga-ocram-ecc"
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| /Documentation/devicetree/bindings/mtd/ |
| D | nand-chip.yaml | 25 nand-ecc-engine:
27 A phandle on the hardware ECC engine if any. There are
29 1/ The ECC engine is part of the NAND controller, in this
31 2/ The ECC engine is part of the NAND part (on-die), in this
33 3/ The ECC engine is external, in this case the phandle should
34 reference the specific ECC engine node.
37 nand-use-soft-ecc-engine:
38 description: Use a software ECC engine.
41 nand-no-ecc-engine:
42 description: Do not use any ECC correction.
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| D | hisi504-nand.txt | 11 - nand-ecc-mode: Support none and hw ecc mode.
17 - nand-ecc-strength: Number of bits to correct per ECC step.
18 - nand-ecc-step-size: Number of data bytes covered by a single ECC step.
20 The following ECC strength and step size are currently supported:
22 - nand-ecc-strength = <16>, nand-ecc-step-size = <1024>
34 nand-ecc-mode = "hw";
35 nand-ecc-strength = <16>;
36 nand-ecc-step-size = <1024>;
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| D | rockchip,nand-controller.yaml | 66 nand-ecc-mode:
69 nand-ecc-step-size:
72 nand-ecc-strength:
75 The ECC configurations that can be supported are as follows.
76 NFC v600 ECC 16, 24, 40, 60
79 NFC v622 ECC 16, 24, 40, 60
82 NFC v800 ECC 16
85 NFC v900 ECC 16, 40, 60, 70
96 The NFC driver need this information to select ECC
100 rockchip,boot-ecc-strength:
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| D | mediatek,nand-ecc-engine.yaml | 4 $id: http://devicetree.org/schemas/mtd/mediatek,nand-ecc-engine.yaml#
7 title: MediaTek(MTK) SoCs NAND ECC engine
13 MTK NAND ECC engine can cowork with MTK raw NAND and SPI NAND controller.
18 - mediatek,mt2701-ecc
19 - mediatek,mt2712-ecc
20 - mediatek,mt7622-ecc
21 - mediatek,mt7986-ecc
25 - description: Base physical address and size of ECC.
29 - description: ECC interrupt
56 bch: ecc@1100e000 {
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| D | nvidia-tegra20-nand.txt | 25 - nand-ecc-mode: String, operation mode of the NAND ecc mode. Currently only
27 - nand-ecc-algo: string, algorithm of NAND ECC.
28 Supported values with "hw" ECC mode are: "rs", "bch".
31 - nand-ecc-strength: integer representing the number of bits to correct
32 per ECC step (always 512). Supported strength using HW ECC
36 - nand-ecc-maximize: See nand-controller.yaml
37 - nand-is-boot-medium: Makes sure only ECC strengths supported by the boot ROM
60 nand-ecc-algo = "bch";
61 nand-ecc-strength = <8>;
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| D | raw-nand-chip.yaml | 16 The ECC strength and ECC step size properties define the user
18 they request the ECC engine to correct {strength} bit errors per
34 nand-ecc-placement:
36 Location of the ECC bytes. This location is unknown by default
37 but can be explicitly set to "oob", if all ECC bytes are
38 known to be stored in the OOB area, or "interleaved" if ECC
44 nand-ecc-mode:
46 Legacy ECC configuration mixing the ECC engine choice and
70 nand-ecc-maximize:
72 Whether or not the ECC strength should be maximized. The
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| D | mxicy,nand-ecc-engine.yaml | 4 $id: http://devicetree.org/schemas/mtd/mxicy,nand-ecc-engine.yaml#
7 title: Macronix NAND ECC engine
14 const: mxicy,nand-ecc-engine-rev3
46 nand-ecc-engine = <&ecc_engine0>;
50 ecc_engine0: ecc@43c40000 {
51 compatible = "mxicy,nand-ecc-engine-rev3";
65 nand-ecc-engine = <&ecc_engine1>;
70 nand-ecc-engine = <&spi_controller1>;
74 ecc_engine1: ecc@43c40000 {
75 compatible = "mxicy,nand-ecc-engine-rev3";
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| D | mediatek,mtk-nfc.yaml | 37 ecc-engine:
38 description: device-tree node of the required ECC engine.
48 nand-ecc-mode:
63 nand-ecc-step-size:
65 nand-ecc-strength:
78 nand-ecc-step-size:
80 nand-ecc-strength:
93 nand-ecc-step-size:
95 nand-ecc-strength:
104 - ecc-engine
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| D | davinci-nand.txt | 42 - nand-ecc-mode: operation mode of the NAND ecc mode. ECC mode
48 - ti,davinci-ecc-bits: used ECC bits, currently supported 1 or 4.
58 - ti,davinci-ecc-mode: operation mode of the NAND ecc mode. ECC mode
86 nand-ecc-mode = "hw";
87 ti,davinci-ecc-bits = <4>;
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| D | denali,nand.yaml | 40 ecc: ECC circuit clock
44 - const: ecc
84 nand-ecc-strength:
88 nand-ecc-step-size:
101 nand-ecc-strength:
106 nand-ecc-step-size:
119 nand-ecc-strength:
123 nand-ecc-step-size:
143 clock-names = "nand", "nand_x", "ecc";
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| D | amlogic,meson-nand.yaml | 49 nand-ecc-mode:
52 nand-ecc-step-size:
55 nand-ecc-strength:
58 The ECC configurations that can be supported are as follows.
70 Number of pages starting from offset 0, where a special ECC
72 code. This ECC configuration uses 384 bytes data blocks.
86 nand-ecc-strength: [nand-ecc-step-size]
87 nand-ecc-step-size: [nand-ecc-strength]
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| D | vf610-nfc.txt | 17 there might be restrictions on maximum rates when using hardware ECC.
29 - nand-ecc-mode: see nand-controller.yaml
31 Required properties for hardware ECC:
32 - nand-ecc-strength: supported strengths are 24 and 32 bit (see nand-controller.yaml)
33 - nand-ecc-step-size: step size equals page size, currently only 2k pages are
54 nand-ecc-mode = "hw";
55 nand-ecc-strength = <32>;
56 nand-ecc-step-size = <2048>;
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| D | brcm,brcmnand.yaml | 131 nand-ecc-step-size:
137 expected for the ECC layout in use. This size, in
145 number of available options for its default ECC
149 brcm,nand-ecc-use-strap:
151 This property requires the host system to get the ECC related
153 the generic NAND ECC settings. This is a common hardware design
154 on BCMBCA based boards. This strap ECC option and generic NAND
155 ECC option can not be specified at the same time.
211 - brcm,nand-ecc-use-strap
216 nand-ecc-strength: false
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| D | marvell,nand-controller.yaml | 74 nand-ecc-step-size:
77 nand-ecc-strength:
80 nand-ecc-mode:
166 nand-ecc-mode = "hw";
169 nand-ecc-strength = <4>;
170 nand-ecc-step-size = <512>;
202 nand-ecc-mode = "hw";
203 nand-ecc-strength = <8>;
204 nand-ecc-step-size = <512>;
222 nand-ecc-mode = "hw";
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| D | atmel-nand.txt | 6 The NAND controller might be connected to an ECC engine.
27 - ecc-engine: phandle to the PMECC block. Only meaningful if the SoC embeds
51 * ECC engine (PMECC) bindings:
70 pmecc: ecc-engine@ffffc070 {
93 ecc-engine = <&pmecc>;
120 and hardware ECC controller if available.
121 If the hardware ECC is PMECC, it should contain address and size for
135 - nand-ecc-mode : String, operation mode of the NAND ecc mode, soft by default.
138 - atmel,has-pmecc : boolean to enable Programmable Multibit ECC hardware,
140 - atmel,pmecc-cap : error correct capability for Programmable Multibit ECC
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| /Documentation/driver-api/ |
| D | mtdnand.rst | 357 Hardware ECC support
363 The nand driver supports three different types of hardware ECC.
367 Hardware ECC generator providing 3 bytes ECC per 256 byte.
371 Hardware ECC generator providing 3 bytes ECC per 512 byte.
375 Hardware ECC generator providing 6 bytes ECC per 512 byte.
379 Hardware ECC generator providing 8 bytes ECC per 512 byte.
396 Transfer the ECC from the hardware to the buffer. If the option
402 In case of an ECC error this function is called for error detection
409 Hardware ECC with syndrome calculation
412 Many hardware ECC implementations provide Reed-Solomon codes and
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| /Documentation/devicetree/bindings/memory-controllers/ |
| D | snps,dw-umctl2-ddrc.yaml | 16 be equipped with SEC/DEC ECC feature if DRAM data bus width is either
20 controller. It has an optional SEC/DEC ECC support in 64- and 32-bits
37 ECC Corrected Error, ECC Uncorrected Error, ECC Address Protection,
48 - description: Common ECC CE/UE/Scrubber/DFI Errors IRQ
50 - const: ecc
51 - description: Individual ECC CE/UE/Scrubber/DFI Errors IRQs
101 interrupt-names = "ecc";
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| D | xlnx,zynq-ddrc-a05.yaml | 14 The Zynq DDR ECC controller has an optional ECC support in half-bus width
15 (16-bit) configuration. It is capable of correcting single bit ECC errors
16 and detecting double bit ECC errors.
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| D | nuvoton,npcm-memory-controller.yaml | 14 The Nuvoton BMC SoC supports DDR4 memory with or without ECC (error correction
18 detection (in-line ECC in which a section (1/8th) of the memory device used to
19 store data is used for ECC storage).
21 Note, the bootloader must configure ECC mode for the memory controller.
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| D | xlnx,zynqmp-ocmc-1.0.yaml | 14 The OCM supports 64-bit wide ECC functionality to detect multi-bit errors
16 being written, the ECC is generated and written into the ECC RAM along with
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| /Documentation/devicetree/bindings/crypto/ |
| D | intel,keembay-ocs-ecc.yaml | 4 $id: http://devicetree.org/schemas/crypto/intel,keembay-ocs-ecc.yaml#
7 title: Intel Keem Bay OCS ECC
15 Cryptography (ECC) device provides hardware acceleration for elliptic curve
20 const: intel,keembay-ocs-ecc
43 compatible = "intel,keembay-ocs-ecc";
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| /Documentation/ABI/testing/ |
| D | sysfs-class-mtd | 123 In the case of ECC NOR, it is the ECC block size.
131 correcting within each region covering an ECC step (see
134 In the case of devices lacking any ECC capability, it is 0.
144 region comprising an ecc step (as reported by the driver) equals
159 more regions comprising an ecc step". The precise definition of
172 This is generally applicable only to NAND flash devices with ECC
173 capability. It is ignored on devices lacking ECC capability;
181 The size of a single region covered by ECC, known as the ECC
182 step. Devices may have several equally sized ECC steps within
186 devices lacking any ECC capability, it is 0.
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| /Documentation/devicetree/bindings/arm/calxeda/ |
| D | l2ecc.yaml | 7 title: Calxeda Highbank L2 cache ECC
10 Binding for the Calxeda Highbank L2 cache controller ECC device.
19 const: calxeda,hb-sregs-l2-ecc
39 compatible = "calxeda,hb-sregs-l2-ecc";
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| /Documentation/devicetree/bindings/spi/ |
| D | mediatek,spi-mtk-snfi.yaml | 17 in single, dual or quad IO mode with pipelined ECC encoding/decoding
18 using the accompanying ECC engine. There should be only one spi
44 nand-ecc-engine:
45 description: device-tree node of the accompanying ECC engine.
57 - nand-ecc-engine
112 nand-ecc-engine = <&bch>;
121 nand-ecc-engine = <&snfi>;
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