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/Documentation/devicetree/bindings/sound/
Dti,tlv320adcx140.yaml1 # SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Texas Instruments TLV320ADCX140 Quad Channel Analog-to-Digital Converter
11 - Andrew Davis <afd@ti.com>
14 The TLV320ADCX140 are multichannel (4-ch analog recording or 8-ch digital
15 PDM microphones recording), high-performance audio, analog-to-digital
28 - ti,tlv320adc3140
29 - ti,tlv320adc5140
30 - ti,tlv320adc6140
[all …]
Dcs35l34.txt5 - compatible : "cirrus,cs35l34"
7 - reg : the I2C address of the device for I2C.
9 - VA-supply, VP-supply : power supplies for the device,
13 - cirrus,boost-vtge-millivolt : Boost Voltage Value. Configures the boost
17 - cirrus,boost-nanohenry: Inductor value for boost converter. The value is
22 - reset-gpios: GPIO used to reset the amplifier.
24 - interrupts : IRQ line info CS35L34.
25 (See Documentation/devicetree/bindings/interrupt-controller/interrupts.txt
28 - cirrus,boost-peak-milliamp : Boost converter peak current limit in mA. The
32 - cirrus,i2s-sdinloc : ADSP SDIN I2S channel location. Indicates whether the
[all …]
/Documentation/devicetree/bindings/gpio/
Dcavium-octeon-gpio.txt4 - compatible: "cavium,octeon-3860-gpio"
8 - reg: The base address of the GPIO unit's register bank.
10 - gpio-controller: This is a GPIO controller.
12 - #gpio-cells: Must be <2>. The first cell is the GPIO pin.
14 - interrupt-controller: The GPIO controller is also an interrupt
18 - #interrupt-cells: Must be <2>. The first cell is the GPIO pin
21 1 - edge triggered on the rising edge.
22 2 - edge triggered on the falling edge
23 4 - level triggered active high.
24 8 - level triggered active low.
[all …]
Dnvidia,tegra20-gpio.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/gpio/nvidia,tegra20-gpio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra GPIO Controller (Tegra20 - Tegra210)
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
16 - enum:
17 - nvidia,tegra20-gpio
18 - nvidia,tegra30-gpio
[all …]
Dbrcm,brcmstb-gpio.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/gpio/brcm,brcmstb-gpio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 The controller's registers are organized as sets of eight 32-bit
15 - Doug Berger <opendmb@gmail.com>
16 - Florian Fainelli <f.fainelli@gmail.com>
21 - enum:
22 - brcm,bcm7445-gpio
23 - const: brcm,brcmstb-gpio
[all …]
Daspeed,sgpio.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Andrew Jeffery <andrew@aj.id.au>
17 - Support interrupt option for each input port and various interrupt
18 sensitivity option (level-high, level-low, edge-high, edge-low)
19 - Support reset tolerance option for each output port
20 - Directly connected to APB bus and its shift clock is from APB bus clock
22 - Co-work with external signal-chained TTL components (74LV165/74LV595)
27 - aspeed,ast2400-sgpio
[all …]
Dsocionext,uniphier-gpio.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/gpio/socionext,uniphier-gpio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Masahiro Yamada <yamada.masahiro@socionext.com>
14 pattern: "^gpio@[0-9a-f]+$"
17 const: socionext,uniphier-gpio
22 gpio-controller: true
24 "#gpio-cells":
27 interrupt-controller: true
[all …]
Dnuvoton,sgpio.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jim LIU <JJLIU0@nuvoton.com>
22 - Support interrupt option for each input port and various interrupt
23 sensitivity options (level-high, level-low, edge-high, edge-low)
24 - ngpios is number of nuvoton,input-ngpios GPIO lines and nuvoton,output-ngpios GPIO lines.
25 nuvoton,input-ngpios GPIO lines is only for GPI.
26 nuvoton,output-ngpios GPIO lines is only for GPO.
31 - nuvoton,npcm750-sgpio
[all …]
/Documentation/devicetree/bindings/power/reset/
Dgpio-restart.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/power/reset/gpio-restart.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Sebastian Reichel <sre@kernel.org>
15 This binding supports level and edge triggered reset. At driver load time, the driver will
17 'open-source' is not found, the GPIO line will be driven in the inactive state. Otherwise its
22 This will also cause an inactive->active edge condition, triggering positive edge triggered
23 reset. After a delay specified by active-delay, the GPIO is set to inactive, thus causing an
24 active->inactive edge, triggering negative edge triggered reset. After a delay specified by
[all …]
/Documentation/devicetree/bindings/spi/
Dicpdas-lp8841-spi-rtc.txt1 * ICP DAS LP-8841 SPI Controller for RTC
3 ICP DAS LP-8841 contains a DS-1302 RTC. RTC is connected to an IO
6 The device uses the standard MicroWire half-duplex transfer timing.
7 Master output is set on low clock and sensed by the RTC on the rising
8 edge. Master input is set by the RTC on the trailing edge and is sensed
9 by the master on low clock.
13 - #address-cells: should be 1
15 - #size-cells: should be 0
17 - compatible: should be "icpdas,lp8841-spi-rtc"
19 - reg: should provide IO memory address
[all …]
/Documentation/devicetree/bindings/interrupt-controller/
Dsnps,archs-idu-intc.txt1 * ARC-HS Interrupt Distribution Unit
9 - compatible: "snps,archs-idu-intc"
10 - interrupt-controller: This is an interrupt controller.
11 - #interrupt-cells: Must be <1> or <2>.
18 - bits[3:0] trigger type and level flags
19 1 = low-to-high edge triggered
20 2 = NOT SUPPORTED (high-to-low edge triggered)
21 4 = active high level-sensitive <<< DEFAULT
22 8 = NOT SUPPORTED (active low level-sensitive)
30 core_intc: core-interrupt-controller {
[all …]
Dnxp,lpc3220-mic.txt4 - compatible: "nxp,lpc3220-mic" or "nxp,lpc3220-sic".
5 - reg: should contain IC registers location and length.
6 - interrupt-controller: identifies the node as an interrupt controller.
7 - #interrupt-cells: the number of cells to define an interrupt, should be 2.
10 IRQ_TYPE_EDGE_RISING = low-to-high edge triggered,
11 IRQ_TYPE_EDGE_FALLING = high-to-low edge triggered,
12 IRQ_TYPE_LEVEL_HIGH = active high level-sensitive,
13 IRQ_TYPE_LEVEL_LOW = active low level-sensitive.
17 - interrupts: empty for MIC interrupt controller, cascaded MIC
23 mic: interrupt-controller@40008000 {
[all …]
Dimg,pdc-intc.txt10 - compatible: Specifies the compatibility list for the interrupt controller.
11 The type shall be <string> and the value shall include "img,pdc-intc".
13 - reg: Specifies the base PDC physical address(s) and size(s) of the
14 addressable register space. The type shall be <prop-encoded-array>.
16 - interrupt-controller: The presence of this property identifies the node
19 - #interrupt-cells: Specifies the number of cells needed to encode an
22 - num-perips: Number of waking peripherals.
24 - num-syswakes: Number of SysWake inputs.
26 - interrupts: List of interrupt specifiers. The first specifier shall be the
34 - <1st-cell>: The interrupt-number that identifies the interrupt source.
[all …]
Datmel,aic.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/atmel,aic.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Nicolas Ferre <nicolas.ferre@microchip.com>
11 - Dharma balasubiramani <dharma.b@microchip.com>
14 The Advanced Interrupt Controller (AIC) is an 8-level priority, individually
16 hundred and twenty-eight interrupt sources.
21 - atmel,at91rm9200-aic
22 - atmel,sama5d2-aic
[all …]
Dopen-pic.txt13 - compatible: Specifies the compatibility list for the PIC. The type
14 shall be <string> and the value shall include "open-pic".
16 - reg: Specifies the base physical address(s) and size(s) of this
17 PIC's addressable register space. The type shall be <prop-encoded-array>.
19 - interrupt-controller: The presence of this property identifies the node
22 - #interrupt-cells: Specifies the number of cells needed to encode an
25 - #address-cells: Specifies the number of cells needed to encode an
27 'interrupt-map' nodes do not have to specify a parent unit address.
31 - pic-no-reset: The presence of this property indicates that the PIC
42 - <1st-cell>: The interrupt-number that identifies the interrupt source.
[all …]
Dsocionext,uniphier-aidet.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/socionext,uniphier-aidet.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 UniPhier AIDET (ARM Interrupt Detector) is an add-on block for ARM GIC
12 rising edge interrupts. The AIDET provides logic inverter to support low
13 level and falling edge interrupts.
16 - Masahiro Yamada <yamada.masahiro@socionext.com>
19 - $ref: /schemas/interrupt-controller.yaml#
24 - socionext,uniphier-ld4-aidet
[all …]
/Documentation/devicetree/bindings/rtc/
Dmaxim-ds1302.txt1 * Maxim/Dallas Semiconductor DS-1302 RTC
5 The device uses the standard MicroWire half-duplex transfer timing.
6 Master output is set on low clock and sensed by the RTC on the rising
7 edge. Master input is set by the RTC on the trailing edge and is sensed
8 by the master on low clock.
12 - compatible : Should be "maxim,ds1302"
16 - reg : Should be address of the device chip select within
19 - spi-max-frequency : DS-1302 has 500 kHz if powered at 2.2V,
22 - spi-3wire : The device has a shared signal IN/OUT line.
24 - spi-lsb-first : DS-1302 requires least significant bit first
[all …]
/Documentation/devicetree/bindings/soc/fsl/cpm_qe/
Dfsl,qe-tsa.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/fsl/cpm_qe/fsl,qe-tsa.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: PowerQUICC QE Time-slot assigner (TSA) controller
10 - Herve Codina <herve.codina@bootlin.com>
13 The TSA is the time-slot assigner that can be found on some PowerQUICC SoC.
14 Its purpose is to route some TDM time-slots to other internal serial
20 - enum:
21 - fsl,mpc8321-tsa
[all …]
/Documentation/arch/arm/pxa/
Dmfp.rst7 MFP stands for Multi-Function Pin, which is the pin-mux logic on PXA3xx and
15 mechanism is introduced from PXA3xx to completely move the pin-mux functions
16 out of the GPIO controller. In addition to pin-mux configurations, the MFP
17 also controls the low power state, driving strength, pull-up/down and event
21 +--------+
22 | |--(GPIO19)--+
24 | |--(GPIO...) |
25 +--------+ |
26 | +---------+
27 +--------+ +------>| |
[all …]
/Documentation/devicetree/bindings/display/panel/
Dpanel-timing.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/panel/panel-timing.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Sam Ravnborg <sam@ravnborg.org>
20 +-------+----------+-------------------------------------+----------+
24 +-------+----------+-------------------------------------+----------+
28 +-------+----------#######################################----------+
33 |<----->|<-------->#<-------+--------------------------->#<-------->|
[all …]
/Documentation/input/devices/
Drotary-encoder.rst2 rotary-encoder - a generic driver for GPIO connected devices
8 --------
11 peripherals with two wires. The outputs are phase-shifted by 90 degrees
15 Some encoders have both outputs low in stable states, others also have
16 a stable state with both outputs high (half-period mode) and some have
17 a stable state in all steps (quarter-period mode).
33 |<-------->|
36 |<-->|
37 one step (half-period mode)
40 one step (quarter-period mode)
[all …]
/Documentation/devicetree/bindings/mips/cavium/
Dcib.txt4 - compatible: "cavium,octeon-7130-cib"
8 - interrupt-controller: This is an interrupt controller.
10 - reg: Two elements consisting of the addresses of the RAW and EN
13 - cavium,max-bits: The index (zero based) of the highest numbered bit
16 - interrupts: The CIU line to which the CIB block is connected.
18 - #interrupt-cells: Must be <2>. The first cell is the bit within the
24 interrupt-controller@107000000e000 {
25 compatible = "cavium,octeon-7130-cib";
28 cavium,max-bits = <23>;
30 interrupt-controller;
[all …]
/Documentation/driver-api/gpio/
Dintro.rst17 A "General Purpose Input/Output" (GPIO) is a flexible software-controlled
25 System-on-Chip (SOC) processors heavily rely on GPIOs. In some cases, every
26 non-dedicated pin can be configured as a GPIO; and most chips have at least
31 Most PC southbridges have a few dozen GPIO-capable pins (with only the BIOS
36 - Output values are writable (high=1, low=0). Some chips also have
38 value might be driven, supporting "wire-OR" and similar schemes for the
41 - Input values are likewise readable (1, 0). Some chips support readback
42 of pins configured as "output", which is very useful in such "wire-OR"
44 input de-glitch/debounce logic, sometimes with software controls.
46 - Inputs can often be used as IRQ signals, often edge triggered but
[all …]
/Documentation/devicetree/bindings/pinctrl/
Dbrcm,bcm2835-gpio.txt7 - compatible: "brcm,bcm2835-gpio"
8 - compatible: should be one of:
9 "brcm,bcm2835-gpio" - BCM2835 compatible pinctrl
10 "brcm,bcm7211-gpio" - BCM7211 compatible pinctrl
11 "brcm,bcm2711-gpio" - BCM2711 compatible pinctrl
12 "brcm,bcm7211-gpio" - BCM7211 compatible pinctrl
13 - reg: Should contain the physical address of the GPIO module's registers.
14 - gpio-controller: Marks the device node as a GPIO controller.
15 - #gpio-cells : Should be two. The first cell is the pin number and the
17 - bit 0 specifies polarity (0 for normal, 1 for inverted)
[all …]
/Documentation/devicetree/bindings/soc/fsl/cpm_qe/cpm/
Dpic.txt4 - fsl,cpm1-pic
5 - only one interrupt cell
6 - fsl,pq1-pic
7 - fsl,cpm2-pic
8 - second interrupt cell is level/sense:
9 - 2 is falling edge
10 - 8 is active low
13 interrupt-controller@10c00 {
14 #interrupt-cells = <2>;
15 interrupt-controller;
[all …]

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