Home
last modified time | relevance | path

Searched full:edma (Results 1 – 17 of 17) sorted by relevance

/Documentation/devicetree/bindings/dma/
Dfsl,edma.yaml4 $id: http://devicetree.org/schemas/dma/fsl,edma.yaml#
7 title: Freescale enhanced Direct Memory Access(eDMA) Controller
10 The eDMA channels have multiplex capability by programmable
22 - fsl,vf610-edma
23 - fsl,imx7ulp-edma
24 - fsl,imx8qm-edma
25 - fsl,imx8ulp-edma
30 - const: fsl,ls1028a-edma
31 - const: fsl,vf610-edma
56 cell 2: bitmask, defined at include/dt-bindings/dma/fsl-edma.h
[all …]
Dti-edma.txt1 Texas Instruments eDMA
20 - reg: Memory map of eDMA CC
24 - ti,tptcs: List of TPTCs associated with the eDMA in the following form:
30 - ti,hwmods: Name of the hwmods associated to the eDMA CC.
40 - ti,edma-memcpy-channels: List of channels allocated to be used for memcpy, iow
42 - ti,edma-reserved-slot-ranges: PaRAM slot ranges which should not be used by
46 Single uint32 for EDMA with 32 channels, array of two uint32 for
47 EDMA with 64 channels. See example and
61 - reg: Memory map of eDMA TC
67 - ti,hwmods: Name of the hwmods associated to the eDMA TC.
[all …]
Dti-dma-crossbar.txt5 "ti,am335x-edma-crossbar" for AM335x and AM437x
8 for ti,dra7-dma-crossbar and <3> for ti,am335x-edma-crossbar.
20 memcpy channels in eDMA.
26 For ti,am335x-edma-crossbar: the meaning of parameters of dmas for clients:
29 When mux 0 is used the DMA channel can be requested directly from edma node.
/Documentation/devicetree/bindings/pci/
Dsnps,dw-pcie-ep.yaml47 with all spaces. Note iATU/eDMA CSRs are indirectly accessible
68 iATU/eDMA registers common for all device functions. It's an
74 normally mapped to the 0x0 address of this region, while eDMA
78 Platform-specific eDMA registers. Some platforms may have eDMA
135 Indicates that the eDMA Tx/Rx transfer is complete or that an
136 error has occurred on the corresponding channel. eDMA can have
137 eight Tx (Write) and Rx (Read) eDMA channels thus supporting up
138 to 16 IRQ signals all together. Write eDMA channels shall go
Dsnps,dw-pcie.yaml56 with all spaces. Note iATU/eDMA CSRs are indirectly accessible
77 iATU/eDMA registers common for all device functions. It's an
83 normally mapped to the 0x0 address of this region, while eDMA
87 Platform-specific eDMA registers. Some platforms may have eDMA
144 Indicates that the eDMA Tx/Rx transfer is complete or that an
145 error has occurred on the corresponding channel. eDMA can have
146 eight Tx (Write) and Rx (Read) eDMA channels thus supporting up
147 to 16 IRQ signals all together. Write eDMA channels shall go
Drockchip-dw-pcie-common.yaml68 eDMA write channel 0 interrupt
70 eDMA write channel 1 interrupt
72 eDMA read channel 0 interrupt
74 eDMA read channel 1 interrupt
Dfsl,imx6q-pcie-ep.yaml42 - description: builtin eDMA interrupter.
147 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; /* eDMA */
Dbaikal,bt1-pcie.yaml43 request and eight Read/Write eDMA IRQ lines are available.
Dsnps,dw-pcie-common.yaml27 iATU/eDMA registers. The particular sub-space is selected by the
/Documentation/devicetree/bindings/crypto/
Domap-aes.txt28 dmas = <&edma 6>,
29 <&edma 5>;
Dti,omap-sham.yaml54 dmas = <&edma 36>;
/Documentation/devicetree/bindings/mmc/
Ddavinci_mmc.txt29 dmas = <&edma 16
30 &edma 17>;
Dti-omap-hsmmc.txt78 dmas = <&edma 24
79 &edma 25>;
/Documentation/devicetree/bindings/mfd/
Dti,am3359-tscadc.yaml77 dmas = <&edma 53 0>, <&edma 57 0>;
/Documentation/devicetree/bindings/iommu/
Dti,omap-iommu.txt29 DSP EDMA MMUs.
/Documentation/devicetree/bindings/mtd/
Dti,gpmc-nand.yaml82 dmas = <&edma 52 0>;
/Documentation/devicetree/bindings/memory-controllers/
Dti,gpmc.yaml167 dmas = <&edma 52 0>;