Searched full:eiointc (Results 1 – 4 of 4) sorted by relevance
| /Documentation/devicetree/bindings/interrupt-controller/ |
| D | loongson,eiointc.yaml | 4 $id: http://devicetree.org/schemas/interrupt-controller/loongson,eiointc.yaml#
23 - loongson,ls2k0500-eiointc
24 - loongson,ls2k2000-eiointc
48 eiointc: interrupt-controller@1fe11600 {
49 compatible = "loongson,ls2k0500-eiointc";
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| /Documentation/arch/loongarch/ |
| D | irq-chip-model.rst | 9 Interrupt Controller), LIOINTC (Legacy I/O Interrupt Controller), EIOINTC (Extended
14 CPUINTC is a per-core controller (in CPU), LIOINTC/EIOINTC/HTVECINTC are per-package
61 interrupts go to PCH-PIC/PCH-LPC/PCH-MSI and gathered by EIOINTC, and then go to
70 | EIOINTC | | LIOINTC | <-- | UARTs |
94 go to PCH-PIC/PCH-LPC and gathered by EIOINTC, and then go to CPUINTC directly::
102 | EIOINTC | | AVECINTC | | LIOINTC | <-- | UARTs |
135 EIOINTC::
185 - EIOINTC is "Extended I/O Interrupts" described in Section 11.2 of
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| /Documentation/translations/zh_TW/arch/loongarch/ |
| D | irq-chip-model.rst | 14 Legacy I/O Interrupt Controller）、EIOINTC（Extended I/O Interrupt Controller）、
18 CPUINTC是一種CPU內部的每個核本地的中斷控制器，LIOINTC/EIOINTC/HTVECINTC是CPU內部的
72 | EIOINTC | | LIOINTC | <-- | UARTs |
105 EIOINTC::
154 - EIOINTC：即《龍芯3A5000處理器使用手冊》第11.2節所描述的“擴展I/O中斷”；
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| /Documentation/translations/zh_CN/arch/loongarch/ |
| D | irq-chip-model.rst | 14 Legacy I/O Interrupt Controller）、EIOINTC（Extended I/O Interrupt Controller）、
18 CPUINTC是一种CPU内部的每个核本地的中断控制器，LIOINTC/EIOINTC/HTVECINTC是CPU内部的
72 | EIOINTC | | LIOINTC | <-- | UARTs |
104 | EIOINTC | | AVECINTC | | LIOINTC | <-- | UARTs |
137 EIOINTC::
186 - EIOINTC：即《龙芯3A5000处理器使用手册》第11.2节所描述的“扩展I/O中断”；
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