Searched +full:enable +full:- +full:method (Results 1 – 25 of 166) sorted by relevance
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| /Documentation/firmware-guide/acpi/ |
| D | method-tracing.rst | 1 .. SPDX-License-Identifier: GPL-2.0
15 method tracing facility.
20 ACPICA provides method tracing capability. And two functions are
24 -----------
28 ACPI_DEBUG_PRINT() macro can be reduced at 2 levels - per-component
30 /sys/module/acpi/parameters/debug_layer) and per-type level (known as
33 But when the particular layer/level is applied to the control method
36 to only enable the particular debug layer/level (normally more detailed)
37 logs when the control method evaluation is started, and disable the
38 detailed logging when the control method evaluation is stopped.
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| /Documentation/devicetree/bindings/arm/cpu-enable-method/ |
| D | marvell,berlin-smp | 2 Secondary CPU enable-method "marvell,berlin-smp" binding
5 This document describes the "marvell,berlin-smp" method for enabling secondary
6 CPUs. To apply to all CPUs, a single "marvell,berlin-smp" enable method should
9 Enable method name: "marvell,berlin-smp"
11 Compatible CPUs: "marvell,pj4b" and "arm,cortex-a9"
15 This enable method needs valid nodes compatible with "arm,cortex-a9-scu" and
16 "marvell,berlin-cpu-ctrl"[1].
21 #address-cells = <1>;
22 #size-cells = <0>;
23 enable-method = "marvell,berlin-smp";
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| D | nuvoton,npcm750-smp | 2 Secondary CPU enable-method "nuvoton,npcm750-smp" binding
5 To apply to all CPUs, a single "nuvoton,npcm750-smp" enable method should be
8 Enable method name: "nuvoton,npcm750-smp"
10 Compatible CPUs: "arm,cortex-a9"
14 This enable method needs valid nodes compatible with "arm,cortex-a9-scu" and
15 "nuvoton,npcm750-gcr".
20 #address-cells = <1>;
21 #size-cells = <0>;
22 enable-method = "nuvoton,npcm750-smp";
26 compatible = "arm,cortex-a9";
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| D | al,alpine-smp | 2 Secondary CPU enable-method "al,alpine-smp" binding
5 This document describes the "al,alpine-smp" method for
7 "al,alpine-smp" enable method should be defined in the
10 Enable method name: "al,alpine-smp"
12 Compatible CPUs: "arm,cortex-a15"
16 This enable method requires valid nodes compatible with
17 "al,alpine-cpu-resume" and "al,alpine-nb-service".
26 - compatible : Should contain "al,alpine-cpu-resume".
27 - reg : Offset and length of the register set for the device
33 #address-cells = <1>;
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| /Documentation/devicetree/bindings/arm/ |
| D | cpus.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
21 with updates for 32-bit and 64-bit ARM systems provided in this document.
30 - square brackets define bitfields, eg reg[7:0] value of the bitfield in
59 On 32-bit ARM v7 or later systems this property is
68 On ARM v8 64-bit systems this property is required
71 * If cpus node's #address-cells property is set to 2
79 * If cpus node's #address-cells property is set to 1
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| D | nvidia,tegra194-ccplex.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/arm/nvidia,tegra194-ccplex.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jonathan Hunter <jonathanh@nvidia.com>
12 - Sumit Gupta <sumitg@nvidia.com>
25 - nvidia,tegra194-ccplex
36 - |
38 compatible = "nvidia,tegra194-ccplex";
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| D | psci.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
15 processors") can be used by Linux to initiate various CPU-centric power
25 r0 => 32-bit Function ID / return value
26 {r1 - r3} => Parameters
40 - description:
44 - description:
52 - const: arm,psci-0.2
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| /Documentation/PCI/ |
| D | pci-iov-howto.rst | 1 .. SPDX-License-Identifier: GPL-2.0
9 :Authors: - Yu Zhao <yu.zhao@intel.com>
10 - Donald Dutile <ddutile@redhat.com>
15 What is SR-IOV
16 --------------
18 Single Root I/O Virtualization (SR-IOV) is a PCI Express Extended
34 How can I enable SR-IOV capability
35 ----------------------------------
37 Multiple methods are available for SR-IOV enablement.
38 In the first method, the device driver (PF driver) will control the
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| /Documentation/devicetree/bindings/arm/bcm/ |
| D | brcm,bcm63138.txt | 1 Broadcom BCM63138 DSL System-on-a-Chip device tree bindings
2 -----------------------------------------------------------
4 Boards compatible with the BCM63138 DSL System-on-a-Chip should have the
13 defined in reset/brcm,bcm63138-pmb.txt for this secondary CPU, and an
14 'enable-method' property.
17 - compatible: should be "brcm,bcm63138-bootlut"
18 - reg: register base address and length for the Boot Lookup table
21 - enable-method: should be "brcm,bcm63138"
24 - enable-method: should be "brcm,bcm63138"
25 - resets: phandle to the relevant PMB controller, one integer indicating the internal
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| /Documentation/devicetree/bindings/ |
| D | numa.txt | 6 1 - Introduction
18 2 - numa-node-id
23 a node id is a 32-bit integer.
26 numa-node-id property which contains the node id of the device.
30 numa-node-id = <0>;
33 numa-node-id = <1>;
36 3 - distance-map
39 The optional device tree node distance-map describes the relative
42 - compatible : Should at least contain "numa-distance-map-v1".
44 - distance-matrix
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| /Documentation/devicetree/bindings/cpu/ |
| D | cpu-topology.txt | 6 1 - Introduction
12 - socket
13 - cluster
14 - core
15 - thread
18 symmetric multi-threading (SMT) is supported or not.
29 Currently, only ARM/RISC-V intend to use this cpu topology binding but it may be
39 2 - cpu-map node
42 The ARM/RISC-V CPU topology is defined within the cpu-map node, which is a direct
46 - cpu-map node
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| D | cpu-capacity.txt | 6 1 - Introduction
15 2 - CPU capacity definition
19 heterogeneity. Such heterogeneity can come from micro-architectural differences
23 capture a first-order approximation of the relative performance of CPUs.
29 * A "single-threaded" or CPU affine benchmark
43 3 - capacity-dmips-mhz
46 capacity-dmips-mhz is an optional cpu node [1] property: u32 value
51 capacity-dmips-mhz property is all-or-nothing: if it is specified for a cpu
54 available, final capacities are calculated by directly using capacity-dmips-
58 4 - Examples
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| D | idle-states.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/cpu/idle-states.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
11 - Anup Patel <anup@brainfault.org>
15 1 - Introduction
18 ARM and RISC-V systems contain HW capable of managing power consumption
19 dynamically, where cores can be put in different low-power states (ranging
22 run-time, can be specified through device tree bindings representing the
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| /Documentation/wmi/ |
| D | acpi-interface.rst | 1 .. SPDX-License-Identifier: GPL-2.0-or-later
13 -------------------
22 -----------
32 0x10 2 2 character method ID or single byte notification ID.
37 The WMI object flags control whether the method or notification ID is used:
39 - 0x1: Data block usage is expensive and must be explicitly enabled/disabled.
40 - 0x2: Data block contains WMI methods.
41 - 0x4: Data block contains ASCIZ string.
42 - 0x8: Data block describes a WMI event, use notification ID instead
43 of method ID.
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| /Documentation/devicetree/bindings/cpufreq/ |
| D | cpufreq-qcom-hw.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/cpufreq/cpufreq-qcom-hw.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
21 - description: v1 of CPUFREQ HW
23 - enum:
24 - qcom,qcm2290-cpufreq-hw
25 - qcom,sc7180-cpufreq-hw
26 - qcom,sdm670-cpufreq-hw
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| D | qcom-cpufreq-nvmem.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/cpufreq/qcom-cpufreq-nvmem.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Ilia Lin <ilia.lin@kernel.org>
28 - qcom,apq8064
29 - qcom,apq8096
30 - qcom,ipq5332
31 - qcom,ipq6018
32 - qcom,ipq8064
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| D | cpufreq-mediatek.txt | 5 - clocks: A list of phandle + clock-specifier pairs for the clocks listed in clock names.
6 - clock-names: Should contain the following:
7 "cpu" - The multiplexer for clock input of CPU cluster.
8 "intermediate" - A parent of "cpu" clock which is used as "intermediate" clock
11 Please refer to Documentation/devicetree/bindings/clock/clock-bindings.txt for
13 - operating-points-v2: Please refer to Documentation/devicetree/bindings/opp/opp-v2.yaml
15 - proc-supply: Regulator for Vproc of CPU cluster.
18 - sram-supply: Regulator for Vsram of CPU cluster. When present, the cpufreq driver
23 - mediatek,cci:
30 - #cooling-cells:
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| /Documentation/translations/zh_TW/arch/arm64/ |
| D | booting.txt | 1 SPDX-License-Identifier: GPL-2.0
15 ---------------------------------------------------------------------
30 ---------------------------------------------------------------------
40 AArch64 異常模型由多個異常級（EL0 - EL3）組成，對於 EL0 和 EL1 異常級
58 -----------------
69 ---------------
81 -------------
91 -------------
111 - 自 v3.17 起，除非另有說明，所有域都是小端模式。
113 - code0/code1 負責跳轉到 stext.
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| /Documentation/translations/zh_CN/arch/arm64/ |
| D | booting.txt | 12 ---------------------------------------------------------------------
26 ---------------------------------------------------------------------
36 AArch64 异常模型由多个异常级（EL0 - EL3）组成，对于 EL0 和 EL1 异常级
54 -----------------
65 ---------------
77 -------------
87 -------------
107 - 自 v3.17 起，除非另有说明，所有域都是小端模式。
109 - code0/code1 负责跳转到 stext.
111 - 当通过 EFI 启动时， 最初 code0/code1 被跳过。
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| /Documentation/devicetree/bindings/power/supply/ |
| D | summit,smb347-charger.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/power/supply/summit,smb347-charger.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - David Heidelberg <david@ixit.cz>
11 - Dmitry Osipenko <digetx@gmail.com>
16 - summit,smb345
17 - summit,smb347
18 - summit,smb358
26 monitored-battery:
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| /Documentation/hwmon/ |
| D | w83791d.rst | 10 Addresses scanned: I2C 0x2c - 0x2f
12 Datasheet: http://www.winbond-usa.com/products/winbond_products/pdfs/PCIC/W83791D_W83791Gb.pdf
22 - Frodo Looijaard <frodol@dds.nl>,
23 - Philip Edelbrock <phil@netroedge.com>,
24 - Mark Studebaker <mdsxyz123@yahoo.com>
28 - Shane Huang (Winbond),
29 - Rudolf Marek <r.marek@assembler.cz>
33 - Sven Anders <anders@anduras.de>
34 - Marc Hulsman <m.hulsman@tudelft.nl>
37 -----------------
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| /Documentation/userspace-api/media/drivers/ |
| D | imx-uapi.rst | 1 .. SPDX-License-Identifier: GPL-2.0
13 ---------
18 - V4L2_EVENT_IMX_FRAME_INTERVAL_ERROR
30 -----------------------------------
33 NTSC/PAL signal re-sync (too little or too many video lines). When
34 this happens, the IPU triggers a mechanism to re-establish vertical
60 - V4L2_CID_IMX_FIM_ENABLE
62 Enable/disable the FIM.
64 - V4L2_CID_IMX_FIM_NUM
70 - V4L2_CID_IMX_FIM_TOLERANCE_MIN
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| D | thp7312.rst | 1 .. SPDX-License-Identifier: GPL-2.0-only
6 The THP7312 driver implements the following driver-specific controls:
9 Enable/Disable auto-adjustment, based on lighting conditions, of the frame
10 rate when auto-exposure is enabled.
13 Set method of auto-focus. Only takes effect when auto-focus is enabled.
15 .. flat-table::
16 :header-rows: 0
17 :stub-columns: 0
20 * - ``0``
21 - Contrast-based auto-focus
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| /Documentation/trace/rv/ |
| D | runtime-verification.rst | 5 Runtime Verification (RV) is a lightweight (yet rigorous) method that
10 Instead of relying on a fine-grained model of a system (e.g., a
11 re-implementation a instruction level), RV works by analyzing the trace of the
17 that require a re-implementation of the entire system in a modeling language.
18 Moreover, given an efficient monitoring method, it is possible execute an
20 events, avoiding, for example, the propagation of a failure on safety-critical
32 system, a set of instances of the monitor (per-cpu monitor, per-task monitor,
36 Linux +---- RV Monitor ----------------------------------+ Formal
38 +-------------------+ +----------------+ +-----------------+
40 | Tracing | -> | Instance(s) | <- | Model |
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| /Documentation/devicetree/bindings/opp/ |
| D | opp-v2-kryo-cpu.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/opp/opp-v2-kryo-cpu.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Ilia Lin <ilia.lin@kernel.org>
13 - $ref: opp-v2-base.yaml#
22 The qcom-cpufreq-nvmem driver reads the efuse value from the SoC to provide
25 operating-points-v2 table when it is parsed by the OPP framework.
30 - operating-points-v2-krait-cpu
31 - operating-points-v2-kryo-cpu
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