Searched +full:engine +full:- +full:specific (Results 1 – 25 of 85) sorted by relevance
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| /Documentation/gpu/ |
| D | drm-usage-stats.rst | 1 .. _drm-client-usage-stats:
8 `fops->show_fdinfo()` as part of the driver specific file operations registered
15 output is split between common and driver specific parts. Having said that,
22 - File shall contain one key value pair per one line of text.
23 - Colon character (`:`) must be used to delimit keys and values.
24 - All keys shall be prefixed with `drm-`.
25 - Whitespace between the delimiter and first non-whitespace character shall be
27 - Keys are not allowed to contain whitespace characters.
28 - Numerical key value pairs can end with optional unit string.
29 - Data type of the value is fixed as defined in the specification.
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| /Documentation/devicetree/bindings/mtd/ |
| D | nand-chip.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mtd/nand-chip.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Miquel Raynal <miquel.raynal@bootlin.com>
13 - $ref: mtd.yaml#
18 SPI-NAND devices are concerned by this description.
23 Contains the chip-select IDs.
25 nand-ecc-engine:
27 A phandle on the hardware ECC engine if any. There are
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| /Documentation/leds/ |
| D | leds-lp55xx.rst | 8 -----------
14 Device attributes for user-space interface
47 To support device specific configurations, special structure
50 - Maximum number of channels
51 - Reset command, chip enable command
52 - Chip specific initialization
53 - Brightness control register access
54 - Setting LED output current
55 - Program memory address access for running patterns
56 - Additional device specific attributes
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| D | leds-lp5562.rst | 15 All four channels can be also controlled using the engine micro programs.
17 For the details, please refer to 'firmware' section in leds-lp55xx.txt
24 Therefore each channel should be mapped to the engine number.
29 Unlike the LP5521/LP5523/55231, LP5562 has unique feature for the engine mux,
35 Red ... Engine 1 (fixed)
36 Green ... Engine 2 (fixed)
37 Blue ... Engine 3 (fixed)
38 White ... Engine 1 or 2 or 3 (selective)
45 the engine selection and loading the firmware.
46 Engine mux has two different mode, RGB and W.
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| /Documentation/devicetree/bindings/fsi/ |
| D | fsi.txt | 1 FSI bus & engine generic device tree bindings
4 The FSI bus is probe-able, so the OS is able to enumerate FSI slaves, and
6 nodes to probed engines. This allows for fsi engines to expose non-probeable
7 busses, which are then exposed by the device tree. For example, an FSI engine
8 that is an I2C master - the I2C bus can be described by the device tree under
9 the engine's device tree node.
13 the fsi-master-* binding specifications.
18 fsi-master {
19 /* top-level of FSI bus topology, bound to an FSI master driver and
22 fsi-slave@<link,id> {
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| /Documentation/driver-api/dmaengine/ |
| D | client.rst | 2 DMA Engine API Guide
7 .. note:: For DMA Engine usage in async_tx please see:
8 ``Documentation/crypto/async-tx-api.rst``
11 Below is a guide to device driver writers on how to use the Slave-DMA API of the
12 DMA Engine. This is applicable only for slave DMA usage only.
19 - Allocate a DMA slave channel
21 - Set slave and controller specific parameters
23 - Get a descriptor for transaction
25 - Submit the transaction
27 - Issue pending requests and wait for callback notification
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| /Documentation/gpu/amdgpu/ |
| D | driver-core.rst | 17 the SoC itself rather than specific IPs. E.g., things like GPU resets
23 SMU, PSP, etc.). Specific components (CPU, GPU, etc.) usually have
32 This was a dedicated IP on older pre-vega chips, but has since
34 have dedicated memory hubs for specific IPs or groups of IPs. We
58 It is described in more details in :ref:`Display Core <amdgpu-display-core>`.
61 This is a multi-purpose DMA engine. The kernel driver uses it for
67 This is the graphics and compute engine, i.e., the block that
69 largest block on the GPU. The 3D pipeline has tons of sub-blocks. In
75 This is the multi-media engine. It handles video and image encode and
76 decode. It's exposed to userspace for user mode drivers (VA-API,
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| /Documentation/arch/powerpc/ |
| D | vas-api.rst | 1 .. SPDX-License-Identifier: GPL-2.0
2 .. _VAS-API:
12 allows both userspace and kernel communicate to co-processor
14 unit comprises of one or more hardware engines or co-processor types
16 userspace applications will have access to only GZIP Compression engine
21 Requests to the GZIP engine must be formatted as a co-processor Request
24 the engine's request queue.
26 The GZIP engine provides two priority levels of requests: Normal and
37 Application access to the GZIP engine is provided through
38 /dev/crypto/nx-gzip device node implemented by the VAS/NX device driver.
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| /Documentation/devicetree/bindings/gpu/host1x/ |
| D | nvidia,tegra210-nvdec.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/gpu/host1x/nvidia,tegra210-nvdec.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
15 - Thierry Reding <treding@gmail.com>
16 - Mikko Perttunen <mperttunen@nvidia.com>
20 pattern: "^nvdec@[0-9a-f]*$"
24 - nvidia,tegra210-nvdec
25 - nvidia,tegra186-nvdec
26 - nvidia,tegra194-nvdec
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| D | nvidia,tegra210-nvenc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/gpu/host1x/nvidia,tegra210-nvenc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
15 - Thierry Reding <treding@gmail.com>
16 - Mikko Perttunen <mperttunen@nvidia.com>
20 pattern: "^nvenc@[0-9a-f]*$"
24 - nvidia,tegra210-nvenc
25 - nvidia,tegra186-nvenc
26 - nvidia,tegra194-nvenc
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| /Documentation/devicetree/bindings/dma/ |
| D | dma-common.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/dma/dma-common.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: DMA Engine Common Properties
10 - Vinod Koul <vkoul@kernel.org>
13 Generic binding to provide a way for a driver using DMA Engine to
20 "#dma-cells":
25 Used to provide DMA controller specific information.
27 dma-channel-mask:
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| D | socionext,uniphier-xdmac.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/dma/socionext,uniphier-xdmac.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 This describes the devicetree bindings for an external DMA engine to perform
11 memory-to-memory or peripheral-to-memory data transfer capable of supporting
15 - Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
18 - $ref: dma-controller.yaml#
22 const: socionext,uniphier-xdmac
30 "#dma-cells":
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| /Documentation/ABI/testing/ |
| D | debugfs-driver-qat | 4 Contact: qat-linux@intel.com
6 received from the FW for each Acceleration Engine
9 <N>: Number of requests sent from Acceleration Engine N to FW and responses
10 Acceleration Engine N received from FW
15 Contact: qat-linux@intel.com
35 Contact: qat-linux@intel.com
44 Contact: qat-linux@intel.com
54 Contact: qat-linux@intel.com
57 Returns 0 when device is healthy or -1 when is unresponsive
66 Contact: qat-linux@intel.com
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| D | sysfs-driver-chromeos-acpi | 32 Returns switch position for Chrome OS specific hardware
56 Returns firmware version for the read-only portion of the
72 Returns type of the GPIO signal for the Chrome OS specific
121 Returns the SHA-1 or SHA-256 hash that is read out of the
122 Management Engine extended registers during boot. The hash
124 Engine firmware has not changed. If Management Engine is not
132 Returns offset in CMOS bank 0 of the verified boot non-volatile
142 Return the size in bytes of the verified boot non-volatile
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| /Documentation/crypto/ |
| D | async-tx-api.rst | 1 .. SPDX-License-Identifier: GPL-2.0
32 bulk memory transfers/transforms with support for inter-transactional
34 the details of different hardware offload engine implementations. Code
43 xor-parity-calculations of the md-raid5 driver using the offload engines
51 operation will be offloaded when an engine is available and carried out
54 operations to be submitted, like xor->copy->xor in the raid5 case. The
64 -----------------------------
69 async_<operation>(<op specific parameters>, struct async_submit_ctl *submit)
72 ------------------------
92 -------------------------
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| /Documentation/gpu/amdgpu/display/ |
| D | dc-glossary.rst | 7 'Documentation/gpu/amdgpu/amdgpu-glossary.rst'; if you cannot find it anywhere,
19 Application-Specific Integrated Circuit
25 Azalia (HD audio DMA engine)
36 * SOCCLK: GPU Engine Clock
49 Cathode Ray Tube Controller - commonly called "Controller" - Generates
68 Display Controller Engine
108 Display Micro-Controller Unit
111 Display Micro-Controller Unit, version B
225 Transition-Minimized Differential Signaling
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| /Documentation/devicetree/bindings/display/mediatek/ |
| D | mediatek,dpi.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - CK Hu <ck.hu@mediatek.com>
11 - Jitao shi <jitao.shi@mediatek.com>
15 subsystem and provides 8-bit RGB/YUV444 or 8/10/10-bit YUV422 pixel data on a
21 - enum:
22 - mediatek,mt2701-dpi
23 - mediatek,mt7623-dpi
24 - mediatek,mt8173-dpi
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| /Documentation/devicetree/bindings/ptp/ |
| D | brcm,ptp-dte.txt | 1 * Broadcom Digital Timing Engine(DTE) based PTP clock
4 - compatible: should contain the core compatibility string
6 compatibility string is to handle SoC specific
9 "brcm,ptp-dte"
11 "brcm,iproc-ptp-dte" - for iproc based SoC's
12 - reg: address and length of the DTE block's NCO registers
16 ptp: ptp-dte@180af650 {
17 compatible = "brcm,iproc-ptp-dte", "brcm,ptp-dte";
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| /Documentation/userspace-api/media/drivers/ |
| D | npcm-video.rst | 1 .. SPDX-License-Identifier: GPL-2.0
8 This driver is used to control the Video Capture/Differentiation (VCD) engine
9 and Encoding Compression Engine (ECE) present on Nuvoton NPCM SoCs. The VCD can
13 Driver-specific Controls
14 ------------------------
19 The VCD engine supports two modes:
21 - COMPLETE mode:
25 - DIFF mode:
33 - ``V4L2_NPCM_CAPTURE_MODE_COMPLETE``: will set VCD to COMPLETE mode.
34 - ``V4L2_NPCM_CAPTURE_MODE_DIFF``: will set VCD to DIFF mode.
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| /Documentation/driver-api/rapidio/ |
| D | mport_cdev.rst | 17 for user-space applications. Most of RapidIO operations are supported through
24 Using available set of ioctl commands user-space applications can perform
27 - Reads and writes from/to configuration registers of mport devices
29 - Reads and writes from/to configuration registers of remote RapidIO devices.
32 - Set RapidIO Destination ID for mport devices (RIO_MPORT_MAINT_HDID_SET)
33 - Set RapidIO Component Tag for mport devices (RIO_MPORT_MAINT_COMPTAG_SET)
34 - Query logical index of mport devices (RIO_MPORT_MAINT_PORT_IDX_GET)
35 - Query capabilities and RapidIO link configuration of mport devices
37 - Enable/Disable reporting of RapidIO doorbell events to user-space applications
39 - Enable/Disable reporting of RIO port-write events to user-space applications
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| /Documentation/devicetree/bindings/net/ |
| D | qcom,bam-dmux.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/qcom,bam-dmux.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Stephan Gerhold <stephan@gerhold.net>
15 or MSM8974. It is built using a simple protocol layer on top of a DMA engine
20 DMA engine). As such it is specific to a firmware version, not a particular
25 const: qcom,bam-dmux
32 - description: Power control
33 - description: Power control acknowledgment
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| /Documentation/devicetree/bindings/mailbox/ |
| D | mediatek,gce-props.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mailbox/mediatek,gce-props.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: MediaTek Global Command Engine Common Properties
10 - Houlong Wei <houlong.wei@mediatek.com>
13 The Global Command Engine (GCE) is an instruction based, multi-threaded,
14 single-core command dispatcher for MediaTek hardware. The Command Queue
18 We use mediatek,gce-mailbox.yaml to define the properties for CMDQ mailbox
23 reserve a mailbox channel to configure GCE hardware register by the specific
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| /Documentation/devicetree/bindings/arm/keystone/ |
| D | keystone.txt | 2 -----------------------------------------------
8 - compatible: All TI specific devices present in Keystone SOC should be in
9 the form "ti,keystone-*". Generic devices like gic, arch_timers, ns16550
14 - Keystone 2 generic SoC:
19 - Keystone 2 Hawking/Kepler
21 - Keystone 2 Lamarr
23 - Keystone 2 Edison
25 - K2G
29 - Keystone 2 Hawking/Kepler EVM
30 compatible = "ti,k2hk-evm", "ti,k2hk", "ti,keystone"
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| /Documentation/devicetree/bindings/mmc/ |
| D | sdhci-msm.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mmc/sdhci-msm.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm SDHCI controller (sdhci-msm)
10 - Bhupesh Sharma <bhupesh.sharma@linaro.org>
19 - enum:
20 - qcom,sdhci-msm-v4
22 - items:
23 - enum:
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| /Documentation/devicetree/bindings/soc/fsl/cpm_qe/ |
| D | fsl,qe-firmware.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/fsl/cpm_qe/fsl,qe-firmware.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale QUICC Engine module Firmware Node
10 - Frank Li <Frank.Li@nxp.com>
18 property, and any firmware-specific properties. The node should be placed
20 fsl,firmware-phandle property. Other QE nodes that need the same firmware
21 should define an fsl,firmware-phandle property that points to the firmware node
30 - fsl,qe-firmware
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