| /Documentation/devicetree/bindings/display/ |
| D | allwinner,sun4i-a10-display-engine.yaml | 4 $id: http://devicetree.org/schemas/display/allwinner,sun4i-a10-display-engine.yaml#
7 title: Allwinner A10 Display Engine Pipeline
14 The display engine pipeline (and its entry point, since it can be
52 - allwinner,sun4i-a10-display-engine
53 - allwinner,sun5i-a10s-display-engine
54 - allwinner,sun5i-a13-display-engine
55 - allwinner,sun6i-a31-display-engine
56 - allwinner,sun6i-a31s-display-engine
57 - allwinner,sun7i-a20-display-engine
58 - allwinner,sun8i-a23-display-engine
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| /Documentation/devicetree/bindings/crypto/ |
| D | qcom,inline-crypto-engine.yaml | 4 $id: http://devicetree.org/schemas/crypto/qcom,inline-crypto-engine.yaml#
7 title: Qualcomm Technologies, Inc. (QTI) Inline Crypto Engine
16 - qcom,sa8775p-inline-crypto-engine
17 - qcom,sc7180-inline-crypto-engine
18 - qcom,sc7280-inline-crypto-engine
19 - qcom,sm8450-inline-crypto-engine
20 - qcom,sm8550-inline-crypto-engine
21 - qcom,sm8650-inline-crypto-engine
22 - const: qcom,inline-crypto-engine
42 compatible = "qcom,sm8550-inline-crypto-engine",
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| D | intel,ixp4xx-crypto.yaml | 8 title: Intel IXP4xx cryptographic engine
14 The Intel IXP4xx cryptographic engine makes use of the IXP4xx NPE
15 (Network Processing Engine). Since it is not a device on its own
27 - description: phandle to the NPE this crypto engine
29 description: phandle to the NPE this crypto engine is using, the cell
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| /Documentation/devicetree/bindings/media/ |
| D | allwinner,sun4i-a10-video-engine.yaml | 4 $id: http://devicetree.org/schemas/media/allwinner,sun4i-a10-video-engine.yaml#
7 title: Allwinner A10 Video Engine
16 - allwinner,sun4i-a10-video-engine
17 - allwinner,sun5i-a13-video-engine
18 - allwinner,sun7i-a20-video-engine
19 - allwinner,sun8i-a33-video-engine
20 - allwinner,sun8i-h3-video-engine
21 - allwinner,sun8i-v3s-video-engine
22 - allwinner,sun8i-r40-video-engine
23 - allwinner,sun20i-d1-video-engine
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| D | aspeed-video.txt | 1 * Device tree bindings for Aspeed Video Engine
3 The Video Engine (VE) embedded in the Aspeed AST2400/2500/2600 SOCs can
7 - compatible: "aspeed,ast2400-video-engine" or
8 "aspeed,ast2500-video-engine" or
9 "aspeed,ast2600-video-engine"
25 video-engine@1e700000 {
26 compatible = "aspeed,ast2500-video-engine";
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| D | nvidia,tegra-vde.yaml | 7 title: NVIDIA Tegra Video Decoder Engine
97 reg = <0x6001a000 0x1000>, /* Syntax Engine */
98 <0x6001b000 0x1000>, /* Video Bitstream Engine */
99 <0x6001c000 0x100>, /* Macroblock Engine */
100 <0x6001c200 0x100>, /* Post-processing Engine */
101 <0x6001c400 0x100>, /* Motion Compensation Engine */
102 <0x6001c600 0x100>, /* Transform Engine */
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| /Documentation/crypto/ |
| D | crypto_engine.rst | 3 Crypto Engine
8 The crypto engine (CE) API is a crypto queue manager.
18 struct crypto_engine engine;
22 The crypto engine only manages asynchronous requests in the form of
25 using container_of. In addition, the engine knows nothing about your
26 structure "``struct your_tfm_ctx``". The engine assumes (requires) the placement
33 engine using ``crypto_engine_stop()`` and destroy the engine with
64 the crypto engine via one of:
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| /Documentation/devicetree/bindings/mtd/ |
| D | nand-chip.yaml | 25 nand-ecc-engine:
27 A phandle on the hardware ECC engine if any. There are
29 1/ The ECC engine is part of the NAND controller, in this
31 2/ The ECC engine is part of the NAND part (on-die), in this
33 3/ The ECC engine is external, in this case the phandle should
34 reference the specific ECC engine node.
37 nand-use-soft-ecc-engine:
38 description: Use a software ECC engine.
41 nand-no-ecc-engine:
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| D | mxicy,nand-ecc-engine.yaml | 4 $id: http://devicetree.org/schemas/mtd/mxicy,nand-ecc-engine.yaml#
7 title: Macronix NAND ECC engine
14 const: mxicy,nand-ecc-engine-rev3
46 nand-ecc-engine = <&ecc_engine0>;
51 compatible = "mxicy,nand-ecc-engine-rev3";
65 nand-ecc-engine = <&ecc_engine1>;
70 nand-ecc-engine = <&spi_controller1>;
75 compatible = "mxicy,nand-ecc-engine-rev3";
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| /Documentation/devicetree/bindings/mips/cavium/ |
| D | dma-engine.txt | 1 * DMA Engine.
3 The Octeon DMA Engine transfers between the Boot Bus and main memory.
4 The DMA Engine will be referred to by phandle by any device that is
12 - reg: The base address of the DMA Engine's register bank.
17 dma0: dma-engine@1180000000100 {
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| /Documentation/devicetree/bindings/spi/ |
| D | adi,axi-spi-engine.yaml | 4 $id: http://devicetree.org/schemas/spi/adi,axi-spi-engine.yaml#
7 title: Analog Devices AXI SPI Engine Controller
10 The AXI SPI Engine controller is part of the SPI Engine framework[1] and
11 allows memory mapped access to the SPI Engine control bus. This allows it
26 const: adi,axi-spi-engine-1.00.a
56 compatible = "adi,axi-spi-engine-1.00.a";
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| D | mediatek,spi-mtk-snfi.yaml | 18 using the accompanying ECC engine. There should be only one spi
44 nand-ecc-engine:
45 description: device-tree node of the accompanying ECC engine.
57 - nand-ecc-engine
112 nand-ecc-engine = <&bch>;
121 nand-ecc-engine = <&snfi>;
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| /Documentation/gpu/ |
| D | drm-usage-stats.rst | 79 - drm-engine-<keystr>: <uint> ns
85 Value shall be in specified time units which the respective GPU engine spent
94 - drm-engine-capacity-<keystr>: <uint>
96 Engine identifier string must be the same as the one specified in the
97 drm-engine-<keystr> tag and shall contain a greater than zero number in case the
98 exported engine corresponds to a group of identical hardware engines.
105 Engine identifier string must be the same as the one specified in the
106 drm-engine-<keystr> tag and shall contain the number of busy cycles for the given
107 engine.
117 Engine identifier string must be the same as the one specified in the
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| D | panfrost.rst | 25 drm-engine-fragment: 1846584880 ns
29 drm-engine-vertex-tiler: 71932239 ns
39 Possible `drm-engine-` key names are: `fragment`, and `vertex-tiler`.
40 `drm-curfreq-` values convey the current operating frequency for that engine.
42 Users must bear in mind that engine and cycle sampling are disabled by default,
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| /Documentation/devicetree/bindings/firmware/ |
| D | intel,ixp4xx-network-processing-engine.yaml | 5 $id: http://devicetree.org/schemas/firmware/intel,ixp4xx-network-processing-engine.yaml#
8 title: Intel IXP4xx Network Processing Engine
14 On the IXP4xx SoCs, the Network Processing Engine (NPE) is a small
25 - const: intel,ixp4xx-network-processing-engine
36 description: Optional node for the embedded crypto engine, the node
37 should be named with the instance number of the NPE engine used for
38 the crypto engine.
51 node should be named with the instance number of the NPE engine
65 compatible = "intel,ixp4xx-network-processing-engine";
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| /Documentation/devicetree/bindings/soc/intel/ |
| D | intel,hps-copy-engine.yaml | 5 $id: http://devicetree.org/schemas/soc/intel/intel,hps-copy-engine.yaml#
8 title: Intel HPS Copy Engine
14 The Intel Hard Processor System (HPS) Copy Engine is an IP block used to copy
21 const: intel,hps-copy-engine
47 compatible = "intel,hps-copy-engine";
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| /Documentation/devicetree/bindings/powerpc/fsl/ |
| D | raideng.txt | 1 * Freescale 85xx RAID Engine nodes
3 RAID Engine nodes are defined to describe on-chip RAID accelerators. Each RAID
4 Engine should have a separate node.
12 This identifies RAID Engine block. 1 in 1.0 represents
30 There must be a sub-node for each job queue present in RAID Engine
31 This node must be a sub-node of the main RAID Engine node
48 There must be a sub-node for each job ring present in RAID Engine
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| /Documentation/leds/ |
| D | leds-lp5562.rst | 15 All four channels can be also controlled using the engine micro programs.
24 Therefore each channel should be mapped to the engine number.
29 Unlike the LP5521/LP5523/55231, LP5562 has unique feature for the engine mux,
35 Red ... Engine 1 (fixed)
36 Green ... Engine 2 (fixed)
37 Blue ... Engine 3 (fixed)
38 White ... Engine 1 or 2 or 3 (selective)
45 the engine selection and loading the firmware.
46 Engine mux has two different mode, RGB and W.
52 echo "RGB" > /sys/bus/i2c/devices/xxxx/engine_mux # engine mux for RGB
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| /Documentation/devicetree/bindings/fsi/ |
| D | fsi.txt | 1 FSI bus & engine generic device tree bindings
7 busses, which are then exposed by the device tree. For example, an FSI engine
9 the engine's device tree node.
26 fsi-slave-engine@<addr> {
27 /* this node defines the engine endpoint & address range, which
32 fsi-slave-engine@<addr> {
95 use a single cell for address and size. Engine nodes represent the endpoint
101 engine@c00 {
112 - that contains an engine that is an I2C master
134 /* FSI engine at 0xc00, using a single page. In this example,
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| D | ibm,p9-sbefifo.yaml | 7 title: IBM FSI-attached SBEFIFO engine
13 The SBEFIFO is an FSI CFAM engine that provides an interface to the
14 POWER processor Self Boot Engine (SBE). This node will always be a child
39 fsi-slave-engine@2400 {
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| /Documentation/netlabel/ |
| D | cipso_ipv4.rst | 2 NetLabel CIPSO/IPv4 Protocol Engine
12 The NetLabel CIPSO/IPv4 protocol engine is based on the IETF Commercial
22 The CIPSO/IPv4 protocol engine applies the CIPSO IP option to packets by
34 The CIPSO/IPv4 protocol engine validates every CIPSO IP option it finds at the
44 The CIPSO/IPv4 protocol engine contains a mechanism to translate CIPSO security
56 CIPSO/IPv4 protocol engine supports this caching mechanism.
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| /Documentation/gpu/amdgpu/ |
| D | driver-core.rst | 61 This is a multi-purpose DMA engine. The kernel driver uses it for
67 This is the graphics and compute engine, i.e., the block that
75 This is the multi-media engine. It handles video and image encode and
86 provides the driver interface to interact with the GFX/Compute engine.
90 GFX/compute engine.
93 This is a new engine for managing queues. This is currently unused.
96 This is another microcontroller in the GFX/Compute engine. It handles
97 power management related functionality within the GFX/Compute engine.
99 and doesn't really have much relation to what the engine does now.
112 and compute queues on the GFX/compute engine. You can use it to
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| /Documentation/driver-api/dmaengine/ |
| D | client.rst | 2 DMA Engine API Guide
7 .. note:: For DMA Engine usage in async_tx please see:
12 DMA Engine. This is applicable only for slave DMA usage only.
79 DMA-engine are:
141 added and the descriptor must then be submitted. Some DMA engine
160 Therefore, it is important that DMA engine drivers drop any
237 engine's metadata area
239 4. use dmaengine_desc_set_metadata_len() to tell the DMA engine the
248 the pointer to the engine's metadata area
263 added, it must be placed on the DMA engine drivers pending queue.
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| /Documentation/devicetree/bindings/ata/ |
| D | cavium-compact-flash.txt | 20 - cavium,dma-engine-handle: Optional, a phandle for the DMA Engine connected
29 cavium,dma-engine-handle = <&dma0>;
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| /Documentation/ABI/testing/ |
| D | debugfs-driver-qat | 6 received from the FW for each Acceleration Engine
9 <N>: Number of requests sent from Acceleration Engine N to FW and responses
10 Acceleration Engine N received from FW
76 Description: (RO) Read returns, for each Acceleration Engine (AE), the number
83 Engine N.
93 random engine and disables the fetching of heartbeat counters.
|