Searched full:engines (Results 1 – 25 of 66) sorted by relevance
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| /Documentation/netlabel/ |
| D | introduction.rst | 15 is composed of three main components, the protocol engines, the communication
18 Protocol Engines
21 The protocol engines are responsible for both applying and retrieving the
25 refrain from calling the protocol engines directly, instead they should use
45 independent interface to the underlying NetLabel protocol engines. In addition
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| /Documentation/devicetree/bindings/fsi/ |
| D | fsi.txt | 5 engines within those slaves. However, we have a facility to match devicetree
6 nodes to probed engines. This allows for fsi engines to expose non-probeable
16 represent the FSI slaves and their slave engines. As a basic outline:
41 adding subordinate device tree nodes as children of FSI engines.
79 Each slave provides an address-space, under which the engines are accessible.
91 FSI engines (devices)
94 Engines are identified by their address under the slaves' address spaces. We
116 additional engines, but they don't necessarily need to be describe in the
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| D | fsi-controller.yaml | 15 various engines such as I2C controllers, SPI controllers, etc.
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| /Documentation/devicetree/bindings/crypto/ |
| D | aspeed,ast2600-acry.yaml | 7 title: ASPEED ACRY ECDSA/RSA Hardware Accelerator Engines
13 The ACRY ECDSA/RSA engines is designed to accelerate the throughput
15 divided into two independent engines - ECC Engine and RSA Engine.
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| D | mv_cesa.txt | 1 Marvell Cryptographic Engines And Security Accelerator
15 - clocks: reference to the crypto engines clocks. This property is only
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| D | aspeed,ast2500-hace.yaml | 7 title: ASPEED HACE hash and crypto Hardware Accelerator Engines
15 divided into two independently engines - Hash Engine and Crypto Engine.
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| D | marvell-cesa.txt | 1 Marvell Cryptographic Engines And Security Accelerator
19 - clocks: reference to the crypto engines clocks. This property is not
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| D | mediatek-crypto.txt | 6 - interrupts: Should contain the five crypto engines interrupts in numeric
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| /Documentation/ABI/testing/ |
| D | sysfs-bus-hsi | 8 engines (APE) with cellular modem engines (CMT) in cellular
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| D | sysfs-bus-fsi | 26 that control access to the internally connected engines. In
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| D | sysfs-driver-habanalabs | 202 Soft-reset will reset only the compute and DMA engines of the
241 the TPC compute engines. Writes to this parameter affect the
253 engines. This property is valid only for the Goya ASIC family
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| /Documentation/misc-devices/ |
| D | mrvl_cn10k_dpi.rst | 12 mailbox logic, and a set of DMA engines & DMA command queues.
20 the DMA engines and VF device's DMA command queues. Also, driver creates
38 a pem port to which DMA engines are wired.
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| /Documentation/gpu/amdgpu/ |
| D | debugging.rst | 56 - SDMA: SDMA engines
57 - VCN: Video encode/decode engines
58 - JPEG: JPEG engines
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| /Documentation/devicetree/bindings/powerpc/4xx/ |
| D | ppc440spe-adma.txt | 5 for DMA engines and Memory Queue Module node. The latter is used
40 for both DMA engines>.
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| /Documentation/gpu/rfc/ |
| D | i915_scheduler.rst | 43 * Features like timeslicing / preemption / virtual engines would
104 * Export engines logical mapping
109 Export engines logical mapping
116 engines in logical order which is a new requirement compared to execlists.
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| /Documentation/arch/powerpc/ |
| D | vas-api.rst | 14 unit comprises of one or more hardware engines or co-processor types
62 access to all GZIP engines in the system. The only valid operations on
79 engines (typically, one per P9 chip) there is just one
130 "Discovery of available VAS engines" section below.
168 that the application can use to copy/paste its CRB to the hardware engines.
190 Discovery of available VAS engines
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| /Documentation/devicetree/bindings/arm/tegra/ |
| D | nvidia,tegra194-cbb.yaml | 34 include all engines using Cortex-R5 (which is ARMv7 CPU cluster) and
35 engines like TSEC (Security co-processor), NVDEC (NVIDIA Video Decoder
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| /Documentation/devicetree/bindings/timestamp/ |
| D | hardware-timestamps-common.yaml | 13 Some devices/SoCs have hardware timestamp engines (HTE) which can use
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| /Documentation/devicetree/bindings/mailbox/ |
| D | brcm,iproc-pdc-mbox.txt | 1 The PDC driver manages data transfer to and from various offload engines
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| D | brcm,iproc-flexrm-mbox.txt | 4 used to submit work to offload engines. An SoC may have multiple FlexRM
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| /Documentation/devicetree/bindings/dma/ |
| D | mv-xor.txt | 1 * Marvell XOR engines
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| D | marvell,xor-v2.yaml | 7 title: Marvell XOR v2 engines
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| /Documentation/gpu/ |
| D | drm-usage-stats.rst | 81 GPUs usually contain multiple execution engines. Each shall be given a stable
98 exported engine corresponds to a group of identical hardware engines.
174 The total size of buffers that are active on one or more engines.
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| /Documentation/accel/ |
| D | introduction.rst | 25 have on-board DRAM (to hold the DL topology), DMA engines and
40 engines. Typically, the common layer in user-space will be the DL frameworks,
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| /Documentation/driver-api/ |
| D | dma-buf.rst | 251 that userspace uses for synchronization across engines or with the CPU, which
330 compute side, like compute units or command submission engines. If both a 3D
348 achieved through e.g. through dedicated engines and minimal compute unit
372 Note that workloads that run on independent hardware like copy engines or other
375 engines to clear or copy memory needed to resolve the page fault.
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