Searched +full:exit +full:- +full:latency (Results 1 – 25 of 51) sorted by relevance
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| /Documentation/devicetree/bindings/power/ |
| D | domain-idle-state.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/power/domain-idle-state.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Ulf Hansson <ulf.hansson@linaro.org>
18 const: domain-idle-states
21 "^(cpu|cluster|domain)-":
29 const: domain-idle-state
31 entry-latency-us:
33 The worst case latency in microseconds required to enter the idle
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| D | power-domain.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/power/power-domain.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Rafael J. Wysocki <rjw@rjwysocki.net>
11 - Kevin Hilman <khilman@kernel.org>
12 - Ulf Hansson <ulf.hansson@linaro.org>
25 \#power-domain-cells property in the PM domain provider node.
29 pattern: "^(power-controller|power-domain|performance-domain)([@-].*)?$"
31 domain-idle-states:
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| /Documentation/devicetree/bindings/cpu/ |
| D | idle-states.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/cpu/idle-states.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
11 - Anup Patel <anup@brainfault.org>
15 1 - Introduction
18 ARM and RISC-V systems contain HW capable of managing power consumption
19 dynamically, where cores can be put in different low-power states (ranging
22 run-time, can be specified through device tree bindings representing the
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| D | cpu-capacity.txt | 6 1 - Introduction
15 2 - CPU capacity definition
19 heterogeneity. Such heterogeneity can come from micro-architectural differences
23 capture a first-order approximation of the relative performance of CPUs.
29 * A "single-threaded" or CPU affine benchmark
43 3 - capacity-dmips-mhz
46 capacity-dmips-mhz is an optional cpu node [1] property: u32 value
51 capacity-dmips-mhz property is all-or-nothing: if it is specified for a cpu
54 available, final capacities are calculated by directly using capacity-dmips-
58 4 - Examples
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| /Documentation/devicetree/bindings/thermal/ |
| D | thermal-idle.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/thermal/thermal-idle.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Daniel Lezcano <daniel.lezcano@linaro.org>
22 const: thermal-idle
24 A thermal-idle node describes the idle cooling device properties to
27 '#cooling-cells':
31 the cooling-maps reference. The first cell is the minimum cooling state
34 duration-us:
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| /Documentation/admin-guide/pm/ |
| D | cpuidle.rst | 1 .. SPDX-License-Identifier: GPL-2.0
27 CPU idle time management is an energy-efficiency feature concerned about using
31 ------------
37 software as individual single-core processors. In other words, a CPU is an
46 Second, if the processor is multi-core, each core in it is able to follow at
61 Finally, each core in a multi-core processor may be able to follow more than one
66 multiple individual single-core "processors", referred to as *hardware threads*
67 (or hyper-threads specifically on Intel hardware), that each can follow one
78 ---------
107 next wakeup event, or there are strict latency constraints preventing any of the
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| D | intel_idle.rst | 1 .. SPDX-License-Identifier: GPL-2.0
24 Documentation/admin-guide/pm/cpuidle.rst if you have not done that yet.]
28 processor's functional blocks into low-power states. That instruction takes two
38 only way to pass early-configuration-time parameters to it is via the kernel
42 .. _intel-idle-enumeration-of-states:
50 as C-states (in the ACPI terminology) or idle states. The list of meaningful
51 ``MWAIT`` hint values and idle states (i.e. low-power configurations of the
56 subsystem (see :ref:`idle-states-representation` in
57 Documentation/admin-guide/pm/cpuidle.rst),
66 `below <intel-idle-parameters_>`_.]
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| /Documentation/devicetree/bindings/arm/ |
| D | psci.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
15 processors") can be used by Linux to initiate various CPU-centric power
25 r0 => 32-bit Function ID / return value
26 {r1 - r3} => Parameters
40 - description:
44 - description:
52 - const: arm,psci-0.2
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| /Documentation/tools/rtla/ |
| D | common_timerlat_options.rst | 1 **-a**, **--auto** *us*
4 while debugging the system. It is equivalent to use **-T** *us* **-s** *us*
5 **-t**. By default, *timerlat* tracer uses FIFO:95 for *timerlat* threads,
6 thus equilavent to **-P** *f:95*.
8 **-p**, **--period** *us*
12 **-i**, **--irq** *us*
14 Stop trace if the *IRQ* latency is higher than the argument in us.
16 **-T**, **--thread** *us*
18 Stop trace if the *Thread* latency is higher than the argument in us.
20 **-s**, **--stack** *us*
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| D | rtla-timerlat-top.rst | 2 rtla-timerlat-top
4 -------------------------------------------
5 Measures the operating system timer latency
6 -------------------------------------------
22 seem with the option **-T**.
35 **--aa-only** *us*
38 Print the auto-analysis if the system hits the stop tracing condition. This option
45 In the example below, the timerlat tracer is dispatched in cpus *1-23* in the
46 automatic trace mode, instructing the tracer to stop if a *40 us* latency or
49 # timerlat -a 40 -c 1-23 -q
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| /Documentation/trace/ |
| D | timerlat-tracer.rst | 6 find sources of wakeup latencies of real-time threads. Like cyclictest,
8 computes a *wakeup latency* value as the difference between the *current
13 -----
28 # _-----=> irqs-off
29 # / _----=> need-resched
30 # | / _---=> hardirq/softirq
31 # || / _--=> preempt-depth
34 # TASK-PID CPU# |||| TIMESTAMP ID CONTEXT LATENCY
36 <idle>-0 [000] d.h1 54.029328: #1 context irq timer_latency 932 ns
37 <...>-867 [000] .... 54.029339: #1 context thread timer_latency 11700 ns
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| D | ftrace.rst | 2 ftrace - Function Tracer
13 - Written for: 2.6.28-rc2
14 - Updated for: 3.10
15 - Updated for: 4.13 - Copyright 2017 VMware Inc. Steven Rostedt
16 - Converted to rst format - Changbin Du <changbin.du@intel.com>
19 ------------
24 performance issues that take place outside of user-space.
28 There's latency tracing to examine what occurs between interrupts
41 ----------------------
43 See Documentation/trace/ftrace-design.rst for details for arch porters and such.
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| D | events-power.rst | 8 - Power state switch which reports events related to suspend (S-states),
9 cpuidle (C-states) and cpufreq (P-states)
10 - System clock related changes
11 - Power domains related changes and transitions
22 -----------------
24 A 'cpu' event class gathers the CPU-related events: cpuidle and
39 Note: the value of '-1' or '4294967295' for state means an exit from the current state,
97 And, there are events used for CPU latency QoS add/update/remove request.
|
| D | osnoise-tracer.rst | 5 In the context of high-performance computing (HPC), the Operating System
9 system. Moreover, hardware-related jobs can also cause noise, for example,
25 the latency. The hwlat detects the NMI execution by observing
26 the entry and exit of a NMI.
31 of hwlat, osnoise takes note of the entry and exit point of any
32 source of interferences, increasing a per-cpu interference counter. The
38 hardware-related noise. In this way, osnoise can account for any
44 -----
59 # _-----=> irqs-off
60 # / _----=> need-resched
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| /Documentation/devicetree/bindings/powerpc/opal/ |
| D | power-mgt.txt | 1 IBM Power-Management Bindings
6 node @power-mgt in the device-tree by the firmware.
9 ----------------
12 - name: The name of the idle state as defined by the firmware.
14 - flags: indicating some aspects of this idle states such as the
15 extent of state-loss, whether timebase is stopped on this
18 - exit-latency: The latency involved in transitioning the state of the
21 - target-residency: The minimum time that the CPU needs to reside in
22 this idle state in order to accrue power-savings
26 ----------------
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| /Documentation/driver-api/usb/ |
| D | usb3-debug-port.rst | 19 3) have a USB 3.0 super-speed A-to-A debugging cable.
30 super-speed port). The debug device is fully compliant with
32 performance full-duplex serial link between the debug target
41 Other uses include simpler, lockless logging instead of a full-
58 "usbcore.autosuspend=-1"
63 should be a USB 3.0 super-speed A-to-A debugging cable.
74 # tail -f /var/log/kern.log
75 [ 1815.983374] usb 4-3: new SuperSpeed USB device number 4 using xhci_hcd
76 [ 1815.999595] usb 4-3: LPM exit latency is zeroed, disabling LPM.
77 [ 1815.999899] usb 4-3: New USB device found, idVendor=1d6b, idProduct=0004
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| /Documentation/devicetree/bindings/memory-controllers/ddr/ |
| D | jedec,lpddr3.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/ddr/jedec,lpddr3.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: LPDDR3 SDRAM compliant to JEDEC JESD209-3
10 - Krzysztof Kozlowski <krzk@kernel.org>
13 - $ref: jedec,lpddr-props.yaml#
18 - items:
19 - enum:
20 - samsung,K3QF2F20DB
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| /Documentation/driver-api/thermal/ |
| D | cpu-idle-cooling.rst | 1 .. SPDX-License-Identifier: GPL-2.0
8 ----------
26 budget lower than the requested one and under-utilize the CPU, thus
27 losing performance. In other words, one OPP under-utilizes the CPU
33 ----------
58 ---------------
70 performance penalty and a fixed latency. Mitigation can be increased
78 |------- -------
81 <------>
82 idle <---------------------->
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| /Documentation/trace/postprocess/ |
| D | trace-vmscan-postprocess.pl | 3 # page reclaim. It makes an attempt to extract some high-level information on
6 # Example usage: trace-vmscan-postprocess.pl < /sys/kernel/tracing/trace_pipe
8 # --read-procstat If the trace lacks process info, get it from /proc
9 # --ignore-pid Aggregate processes of the same name together
31 # Per-order events
43 # High-level events extrapolated from tracepoints
76 # Catch sigint and exit on request
83 if ($current_time - 2 > $sigint_received) {
84 print "SIGINT received, report pending. Hit ctrl-c again to exit\n";
95 exit;
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| /Documentation/arch/x86/ |
| D | resctrl.rst | 1 .. SPDX-License-Identifier: GPL-2.0
9 :Authors: - Fenghua Yu <fenghua.yu@intel.com>
10 - Tony Luck <tony.luck@intel.com>
11 - Vikas Shivappa <vikas.shivappa@intel.com>
38 # mount -t resctrl resctrl [-o cdp[,cdpl2][,mba_MBps][,debug]] /sys/fs/resctrl
57 pseudo-locking is a unique way of using cache control to "pin" or
59 "Cache Pseudo-Locking".
96 own settings for cache use which can over-ride
128 Corresponding region is pseudo-locked. No
131 Indicates if non-contiguous 1s value in CBM is supported.
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| /Documentation/accounting/ |
| D | psi.rst | 4 PSI - Pressure Stall Information
11 latency spikes, throughput losses, and run the risk of OOM kills.
14 either play it safe and under-utilize their hardware resources, or
23 scarcity aids users in sizing workloads to hardware--or provisioning
38 respective file in /proc/pressure/ -- cpu, memory, and io.
48 The "full" line indicates the share of time in which all non-idle
63 (in us) is tracked and exported as well, to allow detection of latency
98 psi metric and deactivates upon exit from the stall state. While system is
116 Notifications to the userspace are rate-limited to one per tracking window.
118 The trigger will de-register when the file descriptor used to define the
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| /Documentation/networking/ |
| D | napi.rst | 1 .. SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
30 of the NAPI instance while the method is the driver-specific event
37 -----------
55 ------------
64 argument - drivers can process completions for any number of Tx
96 or return ``budget - 1``.
101 -------------
109 As mentioned in the :ref:`drv_ctrl` section - napi_disable() and subsequent
111 to be released, not for the poll method to exit. This means that
118 --------------------------
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| D | net_failover.rst | 1 .. SPDX-License-Identifier: GPL-2.0
23 This can be used by paravirtual drivers to enable an alternate low latency
28 virtio-net accelerated datapath: STANDBY mode
31 net_failover enables hypervisor controlled accelerated datapath to virtio-net
35 feature on the virtio-net interface and assign the same MAC address to both
36 virtio-net and VF interfaces.
49 <alias name='ua-backup0'/>
56 <teaming type='transient' persistent='ua-backup0'/>
59 In this configuration, the first device definition is for the virtio-net
63 virtio-net device is set to 'down' to ensure that the 'failover' netdev prefers
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| /Documentation/virt/ |
| D | ne_overview.rst | 1 .. SPDX-License-Identifier: GPL-2.0
17 It runs alongside the VM that spawned it. This setup matches low latency
29 1. An enclave abstraction process - a user space process running in the primary
42 2. The enclave itself - a VM running on the same host as the primary VM that
58 using virtio-vsock [5]. The primary VM has virtio-pci vsock emulated device,
59 while the enclave VM has a virtio-mmio vsock emulated device. The vsock device
60 uses eventfd for signaling. The enclave VM sees the usual interfaces - local
61 APIC and IOAPIC - to get interrupts from virtio-vsock device. The virtio-mmio
84 predefined port - 9000 - to send a heartbeat value - 0xb7. This mechanism is
91 enclave process can exit.
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| /Documentation/RCU/ |
| D | rcubarrier.rst | 10 struct placed within the RCU-protected data structure and another pointer
16 call_rcu(&p->rcu, p_callback);
30 -------------------------------------
37 http://lwn.net/images/ns/kernel/rcu-drop.jpg.
39 We could try placing a synchronize_rcu() in the module-exit code path,
43 One might be tempted to try several back-to-back synchronize_rcu()
45 heavy RCU-callback load, then some of the callbacks might be deferred in
52 -------------
61 Pseudo-code using rcu_barrier() is as follows:
79 If latency is of the essence, workqueues could be used to run these
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