Searched +full:external +full:- +full:clock +full:- +full:frequency (Results 1 – 25 of 140) sorted by relevance
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| /Documentation/devicetree/bindings/clock/ |
| D | nuvoton,npcm750-clk.txt | 1 * Nuvoton NPCM7XX Clock Controller
3 Nuvoton Poleg BMC NPCM7XX contains an integrated clock controller, which
6 External clocks:
10 clk_sysbypck are inputs to the clock controller.
11 clk_rg1refck, clk_rg2refck and clk_xin are external clocks suppling the
12 network. They are set on the device tree, but not used by the clock module. The
17 dt-bindings/clock/nuvoton,npcm7xx-clock.h
20 Required Properties of clock controller:
22 - compatible: "nuvoton,npcm750-clk" : for clock controller of Nuvoton
25 - reg: physical base address of the clock controller and length of
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| D | nvidia,tegra124-car.yaml | 1 # SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/nvidia,tegra124-car.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra Clock and Reset Controller
10 - Jon Hunter <jonathanh@nvidia.com>
11 - Thierry Reding <thierry.reding@gmail.com>
14 The Clock and Reset (CAR) is the HW module responsible for muxing and gating
18 the clock source programming and most of the clock dividers.
20 CLKGEN input signals include the external clock for the reference frequency
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| D | samsung,exynos-ext-clock.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/samsung,exynos-ext-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Samsung SoC external/osc/XXTI/XusbXTI clock
10 - Chanwoo Choi <cw00.choi@samsung.com>
11 - Krzysztof Kozlowski <krzk@kernel.org>
12 - Sylwester Nawrocki <s.nawrocki@samsung.com>
13 - Tomasz Figa <tomasz.figa@gmail.com>
16 Samsung SoCs require an external clock supplied through XXTI or XusbXTI pins.
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| D | samsung,s5pv210-clock.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/samsung,s5pv210-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Samsung S5P6442/S5PC110/S5PV210 SoC clock controller
10 - Chanwoo Choi <cw00.choi@samsung.com>
11 - Krzysztof Kozlowski <krzk@kernel.org>
12 - Sylwester Nawrocki <s.nawrocki@samsung.com>
13 - Tomasz Figa <tomasz.figa@gmail.com>
16 Expected external clocks, defined in DTS as fixed-rate clocks with a matching
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| D | artpec6.txt | 1 * Clock bindings for Axis ARTPEC-6 chip
3 The bindings are based on the clock provider binding in
4 Documentation/devicetree/bindings/clock/clock-bindings.txt
6 External clocks:
7 ----------------
9 There are two external inputs to the main clock controller which should be
10 provided using the common clock bindings.
11 - "sys_refclk": External 50 Mhz oscillator (required)
12 - "i2s_refclk": Alternate audio reference clock (optional).
14 Main clock controller
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| D | pwm-clock.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/clock/pwm-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: An external clock signal driven by a PWM pin.
10 - Philipp Zabel <p.zabel@pengutronix.de>
14 const: pwm-clock
16 '#clock-cells':
19 clock-frequency:
20 description: Exact output frequency, in case the PWM period is not exact
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| D | brcm,bcm2835-cprman.txt | 3 This binding uses the common clock binding:
4 Documentation/devicetree/bindings/clock/clock-bindings.txt
6 The CPRMAN clock controller generates clocks in the audio power domain
7 of the BCM2835. There is a level of PLLs deriving from an external
9 few PLLs, and a level of mostly-generic clock generators sourcing from
11 clock generators, but a few (like the ARM or HDMI) will source from
15 - compatible: should be one of the following,
16 "brcm,bcm2711-cprman"
17 "brcm,bcm2835-cprman"
18 - #clock-cells: Should be <1>. The permitted clock-specifier values can be
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| D | st,stm32-rcc.txt | 1 STMicroelectronics STM32 Reset and Clock Controller
4 The RCC IP is both a reset and a clock controller.
6 Please refer to clock-bindings.txt for common clock controller binding usage.
10 - compatible: Should be:
11 "st,stm32f42xx-rcc"
12 "st,stm32f469-rcc"
13 "st,stm32f746-rcc"
14 "st,stm32f769-rcc"
16 - reg: should be register base and length as documented in the
18 - #reset-cells: 1, see below
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| /Documentation/devicetree/bindings/media/i2c/ |
| D | toshiba,et8ek8.txt | 6 Documentation/devicetree/bindings/media/video-interfaces.txt .
10 --------------------
12 - compatible: "toshiba,et8ek8"
13 - reg: I2C address (0x3e, or an alternative address)
14 - vana-supply: Analogue voltage supply (VANA), 2.8 volts
15 - clocks: External clock to the sensor
16 - clock-frequency: Frequency of the external clock to the sensor. Camera
17 driver will set this frequency on the external clock. The clock frequency is
18 a pre-determined frequency known to be suitable to the board.
19 - reset-gpios: XSHUTDOWN GPIO. The XSHUTDOWN signal is active low. The sensor
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| D | mipi-ccs.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 # Copyright (C) 2014--2020 Intel Corporation
4 ---
5 $id: http://devicetree.org/schemas/media/i2c/mipi-ccs.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Sakari Ailus <sakari.ailus@linux.intel.com>
17 <URL:https://www.mipi.org/specifications/camera-command-set>.
24 Documentation/devicetree/bindings/media/video-interfaces.txt .
29 - items:
30 - const: mipi-ccs-1.1
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| /Documentation/devicetree/bindings/net/can/ |
| D | cc770.txt | 8 - compatible : should be "bosch,cc770" for the CC770 and "intc,82527"
11 - reg : should specify the chip select, address offset and size required
14 - interrupts : property with a value describing the interrupt source
19 - bosch,external-clock-frequency : frequency of the external oscillator
20 clock in Hz. Note that the internal clock frequency used by the
24 - bosch,clock-out-frequency : slock frequency in Hz on the CLKOUT pin.
28 - bosch,slew-rate : slew rate of the CLKOUT signal. If not specified,
31 - bosch,disconnect-rx0-input : see data sheet.
33 - bosch,disconnect-rx1-input : see data sheet.
35 - bosch,disconnect-tx1-output : see data sheet.
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| D | nxp,sja1000.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Wolfgang Grandegger <wg@grandegger.com>
15 - enum:
16 - nxp,sja1000
17 - technologic,sja1000
18 - items:
19 - enum:
20 - renesas,r9a06g032-sja1000 # RZ/N1D
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| /Documentation/devicetree/bindings/iio/imu/ |
| D | adi,adis16480.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Alexandru Tachici <alexandru.tachici@analog.com>
15 - adi,adis16375
16 - adi,adis16480
17 - adi,adis16485
18 - adi,adis16488
19 - adi,adis16490
20 - adi,adis16495-1
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| /Documentation/devicetree/bindings/spi/ |
| D | nxp,sc18is.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Frank Li <Frank.Li@nxp.com>
15 - nxp,sc18is602
16 - nxp,sc18is602b
17 - nxp,sc18is603
22 clock-frequency:
26 external oscillator clock frequency. The clock-frequency property is
27 relevant and needed only if the chip has an external oscillator
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| /Documentation/devicetree/bindings/iio/frequency/ |
| D | adi,adrf6780.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/iio/frequency/adi,adrf6780.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Antoniu Miclaus <antoniu.miclaus@analog.com>
14 radio designs operating in the 5.9 GHz to 23.6 GHz frequency range.
21 - adi,adrf6780
26 spi-max-frequency:
31 Definition of the external clock.
34 clock-names:
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| D | adf4371.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/iio/frequency/adf4371.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Popa Stefan <stefan.popa@analog.com>
14 https://www.analog.com/media/en/technical-documentation/data-sheets/adf4371.pdf
15 https://www.analog.com/media/en/technical-documentation/data-sheets/adf4372.pdf
20 - adi,adf4371
21 - adi,adf4372
28 Definition of the external clock (see clock/clock-bindings.txt)
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| /Documentation/devicetree/bindings/mips/cavium/ |
| D | uctl.txt | 4 - compatible: "cavium,octeon-6335-uctl"
8 - reg: The base address of the UCTL register bank.
10 - #address-cells: Must be <2>.
12 - #size-cells: Must be <2>.
14 - ranges: Empty to signify direct mapping of the children.
16 - refclk-frequency: A single cell containing the reference clock
17 frequency in Hz.
19 - refclk-type: A string describing the reference clock connection
20 either "crystal" or "external".
24 compatible = "cavium,octeon-6335-uctl";
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| /Documentation/devicetree/bindings/net/ieee802154/ |
| D | ca8210.txt | 4 - compatible: Should be "cascoda,ca8210"
5 - reg: Controlling chip select
6 - spi-max-frequency: Maximum clock speed, should be *less than*
8 - spi-cpol: Requires inverted clock polarity
9 - reset-gpio: GPIO attached to reset
10 - irq-gpio: GPIO attached to IRQ
12 - extclock-enable: Include for the ca8210 to route its 16MHz clock
14 - extclock-freq: Frequency in Hz of the external clock
15 - extclock-gpio: GPIO of the ca8210 to output the clock on
21 spi-max-frequency = <3000000>;
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| /Documentation/devicetree/bindings/ptp/ |
| D | fsl,ptp.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale QorIQ 1588 timer based PTP clock
10 - Frank Li <Frank.Li@nxp.com>
15 - enum:
16 - fsl,etsec-ptp
17 - fsl,fman-ptp-timer
18 - fsl,dpaa2-ptp
19 - items:
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| /Documentation/devicetree/bindings/iio/filter/ |
| D | adi,admv8818.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ADMV8818 Digitally Tunable, High-Pass and Low-Pass Filter
10 - Antoniu Miclaus <antoniu.miclaus@analog.com>
14 features a digitally selectable frequency of operation.
15 The device features four independently controlled high-pass
16 filters (HPFs) and four independently controlled low-pass filters
17 (LPFs) that span the 2 GHz to 18 GHz frequency range.
24 - adi,admv8818
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| /Documentation/driver-api/ |
| D | ptp.rst | 1 .. SPDX-License-Identifier: GPL-2.0
4 PTP hardware clock infrastructure for Linux
10 programs, synchronizing Linux with external clocks, and using the
13 A new class driver exports a kernel interface for specific clock
15 complete set of PTP hardware clock functionality.
17 + Basic clock operations
18 - Set time
19 - Get time
20 - Shift the clock by a given offset atomically
21 - Adjust clock frequency
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| /Documentation/devicetree/bindings/usb/ |
| D | octeon-usb.txt | 7 - compatible: must be "cavium,octeon-5750-usbn"
9 - reg: specifies the physical base address of the USBN block and
12 - #address-cells: specifies the number of cells needed to encode an
15 - #size-cells: specifies the number of cells used to represent the size
18 - ranges: specifies the translation between child address space and parent
21 - clock-frequency: speed of the USB reference clock. Allowed values are
24 - cavium,refclk-type: type of the USB reference clock. Allowed values are
25 "crystal" or "external".
27 - refclk-frequency: deprecated, use "clock-frequency".
29 - refclk-type: deprecated, use "cavium,refclk-type".
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| /Documentation/devicetree/bindings/iio/adc/ |
| D | st,stm32-dfsdm-adc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/iio/adc/st,stm32-dfsdm-adc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Fabrice Gasnier <fabrice.gasnier@foss.st.com>
11 - Olivier Moysan <olivier.moysan@foss.st.com>
14 STM32 DFSDM ADC is a sigma delta analog-to-digital converter dedicated to
15 interface external sigma delta modulators to STM32 micro controllers.
17 - Sigma delta modulators (motor control, metering...)
18 - PDM microphones (audio digital microphone)
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| /Documentation/devicetree/bindings/peci/ |
| D | peci-aspeed.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/peci/peci-aspeed.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Iwona Winiarska <iwona.winiarska@intel.com>
11 - Jae Hyun Yoo <jae.hyun.yoo@linux.intel.com>
14 - $ref: peci-controller.yaml#
19 - aspeed,ast2400-peci
20 - aspeed,ast2500-peci
21 - aspeed,ast2600-peci
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| /Documentation/devicetree/bindings/net/wireless/ |
| D | ti,wlcore.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Tony Lindgren <tony@atomide.com>
14 Note that the *-clock-frequency properties assume internal clocks. In case
15 of external clocks, new bindings (for parsing the clock nodes) have to be
21 - ti,wl1271
22 - ti,wl1273
23 - ti,wl1281
24 - ti,wl1283
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