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/Documentation/devicetree/bindings/interrupt-controller/
Datmel,aic.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/atmel,aic.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Nicolas Ferre <nicolas.ferre@microchip.com>
11 - Dharma balasubiramani <dharma.b@microchip.com>
14 The Advanced Interrupt Controller (AIC) is an 8-level priority, individually
16 hundred and twenty-eight interrupt sources.
21 - atmel,at91rm9200-aic
22 - atmel,sama5d2-aic
[all …]
Dst,stih407-irq-syscfg.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/st,stih407-irq-syscfg.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: STMicroelectronics STi System Configuration Controlled IRQs
10 - Patrice Chotard <patrice.chotard@foss.st.com>
13 On STi based systems; External, CTI (Core Sight), PMU (Performance
14 Management), and PL310 L2 Cache IRQs are controlled using System
19 const: st,stih407-irq-syscfg
22 description: Phandle to Cortex-A9 IRQ system config registers
[all …]
Dmicrochip,pic32-evic.txt5 It handles all internal and external interrupts. This controller exists outside
9 External interrupts have a software configurable edge polarity. Non external
14 -------------------
16 - compatible: Should be "microchip,pic32mzda-evic"
17 - reg: Specifies physical base address and size of register range.
18 - interrupt-controller: Identifies the node as an interrupt controller.
19 - #interrupt cells: Specifies the number of cells used to encode an interrupt
25 hw_irq - represents the hardware interrupt number as in the data sheet.
26 irq_type - is used to describe the type and polarity of an interrupt. For
28 IRQ_TYPE_LEVEL_HIGH for persistent interrupts. For external interrupts use
[all …]
Dmicrochip,sama7g5-eic.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/microchip,sama7g5-eic.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Microchip External Interrupt Controller
10 - Claudiu Beznea <claudiu.beznea@microchip.com>
14 support for handling up to 2 external interrupt lines.
19 - microchip,sama7g5-eic
24 interrupt-controller: true
26 '#interrupt-cells':
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Dti,pruss-intc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/ti,pruss-intc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: TI PRU-ICSS Local Interrupt Controller
10 - Suman Anna <s-anna@ti.com>
13 Each PRU-ICSS has a single interrupt controller instance that is common
17 various other PRUSS internal and external peripherals. The first 2 output
19 remaining 8 (2 through 9) connected to external interrupt controllers
22 The property "ti,irqs-reserved" is used for denoting the connection
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Dactions,owl-sirq.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/actions,owl-sirq.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
11 - Cristian Ciocaltea <cristian.ciocaltea@gmail.com>
15 and S900) and provides support for handling up to 3 external interrupt lines.
20 - actions,s500-sirq
21 - actions,s700-sirq
22 - actions,s900-sirq
[all …]
Dsnps,archs-idu-intc.txt1 * ARC-HS Interrupt Distribution Unit
4 for dynamic IRQ routing, load balancing of common/external IRQs towards core
9 - compatible: "snps,archs-idu-intc"
10 - interrupt-controller: This is an interrupt controller.
11 - #interrupt-cells: Must be <1> or <2>.
18 - bits[3:0] trigger type and level flags
19 1 = low-to-high edge triggered
20 2 = NOT SUPPORTED (high-to-low edge triggered)
21 4 = active high level-sensitive <<< DEFAULT
22 8 = NOT SUPPORTED (active low level-sensitive)
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/Documentation/mhi/
Dtopology.rst1 .. SPDX-License-Identifier: GPL-2.0
11 --------------
14 such as the external modems and WiFi chipsets. It is also the MHI bus master
23 * Configures IRQs, IOMMU, and IOMEM
30 ----------
33 for bi-directional communication. Once MHI is in powered on state, the MHI
43 ----------
46 driver sends and receives the upper-layer protocol packets like IP packets,
/Documentation/devicetree/bindings/net/
Dapm-xgene-enet.txt1 APM X-Gene SoC Ethernet nodes
3 Ethernet nodes are defined to describe on-chip ethernet interfaces in
4 APM X-Gene SoC.
7 - compatible: Should state binding information from the following list,
8 - "apm,xgene-enet": RGMII based 1G interface
9 - "apm,xgene1-sgenet": SGMII based 1G interface
10 - "apm,xgene1-xgenet": XFI based 10G interface
11 - reg: Address and length of the register set for the device. It contains the
12 information of registers in the same order as described by reg-names
13 - reg-names: Should contain the register set names
[all …]
/Documentation/driver-api/gpio/
Ddriver.rst26 between 0 and n-1, n being the number of GPIOs managed by the chip.
29 example if a system uses a memory-mapped set of I/O-registers where 32 GPIO
30 lines are handled by one bit per line in a 32-bit register, it makes sense to
44 So for example one platform could use global numbers 32-159 for GPIOs, with a
46 global numbers 0..63 with one set of GPIO controllers, 64-79 with another type
47 of GPIO controller, and on one particular board 80-95 with an FPGA. The legacy
49 2000-2063 to identify GPIO lines in a bank of I2C GPIO expanders.
60 - methods to establish GPIO line direction
61 - methods used to access GPIO line values
62 - method to set electrical configuration for a given GPIO line
[all …]
Dintro.rst17 A "General Purpose Input/Output" (GPIO) is a flexible software-controlled
21 (BGA) packages. Board schematics show which external hardware connects to
25 System-on-Chip (SOC) processors heavily rely on GPIOs. In some cases, every
26 non-dedicated pin can be configured as a GPIO; and most chips have at least
31 Most PC southbridges have a few dozen GPIO-capable pins (with only the BIOS
36 - Output values are writable (high=1, low=0). Some chips also have
38 value might be driven, supporting "wire-OR" and similar schemes for the
41 - Input values are likewise readable (1, 0). Some chips support readback
42 of pins configured as "output", which is very useful in such "wire-OR"
44 input de-glitch/debounce logic, sometimes with software controls.
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/Documentation/devicetree/bindings/powerpc/fsl/
Dmpc5200.txt2 ----------------------------
4 (c) 2006-2009 Secret Lab Technologies Ltd
8 ------------------
9 For mpc5200 on-chip devices, the format for each compatible value is
10 <chip>-<device>[-<mode>]. The OS should be able to match a device driver
21 "fsl,mpc5200-<device>".
29 compatible = "fsl,mpc5200b-<device>","fsl,mpc5200-<device>";
34 ie. ethernet on mpc5200: compatible = "fsl,mpc5200-fec";
35 ethernet on mpc5200b: compatible = "fsl,mpc5200b-fec", "fsl,mpc5200-fec";
39 "fsl,mpc5200-psc-i2s", not "fsl,mpc5200-i2s". This convention is chosen to
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/Documentation/trace/
Dtimerlat-tracer.rst6 find sources of wakeup latencies of real-time threads. Like cyclictest,
13 -----
28 # _-----=> irqs-off
29 # / _----=> need-resched
30 # | / _---=> hardirq/softirq
31 # || / _--=> preempt-depth
34 # TASK-PID CPU# |||| TIMESTAMP ID CONTEXT LATENCY
36 <idle>-0 [000] d.h1 54.029328: #1 context irq timer_latency 932 ns
37 <...>-867 [000] .... 54.029339: #1 context thread timer_latency 11700 ns
38 <idle>-0 [001] dNh1 54.029346: #1 context irq timer_latency 2833 ns
[all …]
Dftrace.rst2 ftrace - Function Tracer
13 - Written for: 2.6.28-rc2
14 - Updated for: 3.10
15 - Updated for: 4.13 - Copyright 2017 VMware Inc. Steven Rostedt
16 - Converted to rst format - Changbin Du <changbin.du@intel.com>
19 ------------
24 performance issues that take place outside of user-space.
41 ----------------------
43 See Documentation/trace/ftrace-design.rst for details for arch porters and such.
47 ---------------
[all …]
/Documentation/devicetree/bindings/input/
Ddlg,da7280.txt4 - compatible: Should be "dlg,da7280".
5 - reg: Specifies the I2C slave address.
7 - interrupt-parent : Specifies the phandle of the interrupt controller to
8 which the IRQs from DA7280 are delivered to.
10 - dlg,actuator-type: Set Actuator type. it should be one of:
11 "LRA" - Linear Resonance Actuator type.
12 "ERM-bar" - Bar type Eccentric Rotating Mass.
13 "ERM-coin" - Coin type Eccentric Rotating Mass.
15 - dlg,const-op-mode: Haptic operation mode for FF_CONSTANT.
17 1 - Direct register override(DRO) mode triggered by i2c(default),
[all …]
/Documentation/admin-guide/
Drtc.rst8 the local time zone or daylight savings time -- unless they dual boot
9 with MS-Windows -- but will instead be set to Coordinated Universal Time
12 The newest non-PC hardware tends to just count seconds, like the time(2)
16 Linux has two largely-compatible userspace RTC API families you may
20 so it's not very portable to non-x86 systems.
35 Old PC/AT-Compatible driver: /dev/rtc
36 --------------------------------------
44 a few ways (enabling longer alarm periods, and wake-from-hibernate).
59 the type of interrupt (update-done, alarm-rang, or periodic) that was
61 the last read. Status information is reported through the pseudo-file
[all …]
Dkernel-parameters.txt16 force -- enable ACPI if default was off
17 on -- enable ACPI but allow fallback to DT [arm64,riscv64]
18 off -- disable ACPI if default was on
19 noirq -- do not use ACPI for IRQ routing
20 strict -- Be less tolerant of platforms that are not
22 rsdt -- prefer RSDT over (default) XSDT
23 copy_dsdt -- copy DSDT to memory
24 nospcr -- disable console in ACPI SPCR table as
41 If set to vendor, prefer vendor-specific driver
73 Documentation/firmware-guide/acpi/debug.rst for more information about
[all …]
/Documentation/networking/device_drivers/ethernet/mellanox/mlx5/
Dswitchdev.rst1 .. SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB
19 - Change device to switchdev mode::
23 - Attach mlx5 switchdev representor 'enp8s0f0' to bridge netdev 'bridge1'::
28 -----
32 - VLAN filtering (including multiple VLANs per port)::
35 $ bridge vlan add dev enp8s0f0 vid 2-3
37 - VLAN push on bridge ingress::
41 - VLAN pop on bridge egress::
48 Subfunction which are spawned over the E-switch are created only with devlink
55 - Create SF::
[all …]
/Documentation/devicetree/bindings/pci/
Dsnps,dw-pcie-ep.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/pci/snps,dw-pcie-ep.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jingoo Han <jingoohan1@gmail.com>
11 - Gustavo Pimentel <gustavo.pimentel@synopsys.com>
16 # Please create a separate DT-schema for your DWC PCIe Endpoint controller
17 # and make sure it's assigned with the vendor-specific compatible string.
21 const: snps,dw-pcie-ep
23 - compatible
[all …]
/Documentation/virt/kvm/devices/
Dxive.rst1 .. SPDX-License-Identifier: GPL-2.0
4 POWER9 eXternal Interrupt Virtualization Engine (XIVE Gen1)
8 - KVM_DEV_TYPE_XIVE POWER9 XIVE Interrupt Controller generation 1
32 - Interrupt Pending Buffer (IPB)
33 - Current Processor Priority (CPPR)
34 - Notification Source Register (NSR)
49 3. Device pass-through
51 When a device is passed-through into the guest, the source
56 kvmppc_xive_clr_mapped() are called when the device HW irqs are
61 interrupt of the device being passed-through or the initial IPI ESB
[all …]
/Documentation/devicetree/bindings/soc/ti/
Dti,pruss.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 TI Programmable Real-Time Unit and Industrial Communication Subsystem
11 - Suman Anna <s-anna@ti.com>
15 The Programmable Real-Time Unit and Industrial Communication Subsystem
16 (PRU-ICSS a.k.a. PRUSS) is present on various TI SoCs such as AM335x, AM437x,
17 Keystone 66AK2G, OMAP-L138/DA850 etc. A PRUSS consists of dual 32-bit RISC
18 cores (Programmable Real-Time Units, or PRUs), shared RAM, data and
23 peripheral interfaces, fast real-time responses, or specialized data handling.
[all …]
/Documentation/driver-api/pm/
Ddevices.rst1 .. SPDX-License-Identifier: GPL-2.0
10 :Copyright: |copy| 2010-2011 Rafael J. Wysocki <rjw@sisk.pl>, Novell Inc.
18 management (PM) code is also driver-specific. Most drivers will do very
22 This writeup gives an overview of how drivers interact with system-wide
25 background for the domain-specific work you'd do with any specific driver.
31 Drivers will use one or both of these models to put devices into low-power
36 Drivers can enter low-power states as part of entering system-wide
37 low-power states like "suspend" (also known as "suspend-to-RAM"), or
39 "suspend-to-disk").
42 by implementing various role-specific suspend and resume methods to
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/Documentation/driver-api/driver-model/
Dplatform.rst6 platform bus: platform_device, and platform_driver. This pseudo-bus
8 like those used to integrate peripherals on many system-on-chip
16 entities in the system. This includes legacy port-based devices and
18 into system-on-chip platforms. What they usually have in common
24 list of resources such as addresses and IRQs::
62 Or, in common situations where the device is known not to be hot-pluggable,
86 As a rule, platform specific (and often board-specific) setup code will
95 might be configured to work with an external network adapter that might not
102 a kernel for a specific target board. Such board-specific kernels are
113 calls to clk_get(&pdev->dev, clock_name) return them as needed.
[all …]
/Documentation/networking/device_drivers/hamradio/
Dz8530drv.rst1 .. SPDX-License-Identifier: GPL-2.0
5 SCC.C - Linux driver for Z8530 based HDLC cards for AX.25
14 1. ftp://ftp.ccac.rwth-aachen.de/pub/jr/z8530drv-utils_3.0-3.tar.gz
16 2. ftp://ftp.pspt.fi/pub/ham/linux/ax25/z8530drv-utils_3.0-3.tar.gz
41 AX.25-HOWTO on how to emulate a KISS TNC on network device drivers.
54 please read 'man insmod' that comes with module-init-tools.
64 of your rc.*-files. This has to be done BEFORE you can
92 - this is just a delimiter to make sccinit a bit simpler to
96 - the address of the data port A of this Z8530 (needed)
98 - the address of the control port A (needed)
[all …]
/Documentation/arch/x86/
Dresctrl.rst1 .. SPDX-License-Identifier: GPL-2.0
9 :Authors: - Fenghua Yu <fenghua.yu@intel.com>
10 - Tony Luck <tony.luck@intel.com>
11 - Vikas Shivappa <vikas.shivappa@intel.com>
38 # mount -t resctrl resctrl [-o cdp[,cdpl2][,mba_MBps][,debug]] /sys/fs/resctrl
57 pseudo-locking is a unique way of using cache control to "pin" or
59 "Cache Pseudo-Locking".
96 own settings for cache use which can over-ride
128 Corresponding region is pseudo-locked. No
131 Indicates if non-contiguous 1s value in CBM is supported.
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