Searched +full:external +full:- +full:memory +full:- +full:controller (Results 1 – 25 of 131) sorted by relevance
123456
| /Documentation/devicetree/bindings/memory-controllers/ |
| D | nvidia,tegra210-emc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra210-emc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra210 SoC External Memory Controller
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
14 The EMC interfaces with the off-chip SDRAM to service the request stream
15 sent from the memory controller.
19 const: nvidia,tegra210-emc
[all …]
|
| D | nvidia,tegra186-mc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra186-mc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra186 (and later) SoC Memory Controller
10 - Jon Hunter <jonathanh@nvidia.com>
11 - Thierry Reding <thierry.reding@gmail.com>
14 The NVIDIA Tegra186 SoC features a 128 bit memory controller that is split
16 handles memory requests for 40-bit virtual addresses from internal clients
17 and arbitrates among them to allocate memory bandwidth.
[all …]
|
| D | st,stm32-fmc2-ebi.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/st,stm32-fmc2-ebi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: STMicroelectronics Flexible Memory Controller 2 (FMC2)
11 asynchronous static devices (such as PSNOR, PSRAM or other memory-mapped
14 - to translate AXI transactions into the appropriate external device
16 - to meet the access time requirements of the external devices
17 All external devices share the addresses, data and control signals with the
18 controller. Each external device is accessed by means of a unique Chip
[all …]
|
| D | samsung,s5pv210-dmc.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/samsung,s5pv210-dmc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Samsung S5Pv210 SoC Dynamic Memory Controller
10 - Krzysztof Kozlowski <krzk@kernel.org>
13 Dynamic Memory Controller interfaces external JEDEC DDR-type SDRAM.
17 const: samsung,s5pv210-dmc
23 - compatible
24 - reg
[all …]
|
| D | nvidia,tegra20-emc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra20-emc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra20 SoC External Memory Controller
10 - Dmitry Osipenko <digetx@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
12 - Thierry Reding <thierry.reding@gmail.com>
15 The External Memory Controller (EMC) interfaces with the off-chip SDRAM to
16 service the request stream sent from Memory Controller. The EMC also has
[all …]
|
| /Documentation/devicetree/bindings/clock/ |
| D | nvidia,tegra124-car.yaml | 1 # SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/nvidia,tegra124-car.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra Clock and Reset Controller
10 - Jon Hunter <jonathanh@nvidia.com>
11 - Thierry Reding <thierry.reding@gmail.com>
20 CLKGEN input signals include the external clock for the reference frequency
21 (12 MHz, 26 MHz) and the external clock for the Real Time Clock (32.768 KHz).
31 - nvidia,tegra124-car
[all …]
|
| D | nuvoton,npcm750-clk.txt | 1 * Nuvoton NPCM7XX Clock Controller
3 Nuvoton Poleg BMC NPCM7XX contains an integrated clock controller, which
6 External clocks:
10 clk_sysbypck are inputs to the clock controller.
11 clk_rg1refck, clk_rg2refck and clk_xin are external clocks suppling the
17 dt-bindings/clock/nuvoton,npcm7xx-clock.h
20 Required Properties of clock controller:
22 - compatible: "nuvoton,npcm750-clk" : for clock controller of Nuvoton
25 - reg: physical base address of the clock controller and length of
26 memory mapped region.
[all …]
|
| D | rockchip,rk3328-cru.txt | 3 The RK3328 clock controller generates and supplies clock to various
4 controllers within the SoC and also implements a reset controller for SoC
9 - compatible: should be "rockchip,rk3328-cru"
10 - reg: physical base address of the controller and length of memory mapped
12 - #clock-cells: should be 1.
13 - #reset-cells: should be 1.
17 - rockchip,grf: phandle to the syscon managing the "general register files"
22 preprocessor macros in the dt-bindings/clock/rk3328-cru.h headers and can be
26 External clocks:
30 clock-output-names:
[all …]
|
| D | samsung,exynos850-clock.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/samsung,exynos850-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Samsung Exynos850 SoC clock controller
10 - Sam Protsenko <semen.protsenko@linaro.org>
11 - Chanwoo Choi <cw00.choi@samsung.com>
12 - Krzysztof Kozlowski <krzk@kernel.org>
13 - Sylwester Nawrocki <s.nawrocki@samsung.com>
14 - Tomasz Figa <tomasz.figa@gmail.com>
[all …]
|
| /Documentation/devicetree/bindings/net/can/ |
| D | cc770.txt | 1 Memory mapped Bosch CC770 and Intel AN82527 CAN controller
3 Note: The CC770 is a CAN controller from Bosch, which is 100%
8 - compatible : should be "bosch,cc770" for the CC770 and "intc,82527"
11 - reg : should specify the chip select, address offset and size required
12 to map the registers of the controller. The size is usually 0x80.
14 - interrupts : property with a value describing the interrupt source
15 (number and sensitivity) required for the controller.
19 - bosch,external-clock-frequency : frequency of the external oscillator
21 controller is half of that value. If not specified, a default
24 - bosch,clock-out-frequency : slock frequency in Hz on the CLKOUT pin.
[all …]
|
| /Documentation/devicetree/bindings/dma/ |
| D | socionext,uniphier-xdmac.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/dma/socionext,uniphier-xdmac.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Socionext UniPhier external DMA controller
10 This describes the devicetree bindings for an external DMA engine to perform
11 memory-to-memory or peripheral-to-memory data transfer capable of supporting
15 - Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
18 - $ref: dma-controller.yaml#
22 const: socionext,uniphier-xdmac
[all …]
|
| /Documentation/devicetree/bindings/devfreq/ |
| D | nvidia,tegra30-actmon.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/devfreq/nvidia,tegra30-actmon.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Dmitry Osipenko <digetx@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
12 - Thierry Reding <thierry.reding@gmail.com>
17 which the external memory needs to be clocked in order to serve all requests
23 - nvidia,tegra30-actmon
24 - nvidia,tegra114-actmon
[all …]
|
| /Documentation/devicetree/bindings/bus/ |
| D | nvidia,tegra20-gmi.txt | 1 Device tree bindings for NVIDIA Tegra Generic Memory Interface bus
3 The Generic Memory Interface bus enables memory transfers between internal and
4 external memory. Can be used to attach various high speed devices such as
10 - compatible : Should contain one of the following:
11 For Tegra20 must contain "nvidia,tegra20-gmi".
12 For Tegra30 must contain "nvidia,tegra30-gmi".
13 - reg: Should contain GMI controller registers location and length.
14 - clocks: Must contain an entry for each entry in clock-names.
15 - clock-names: Must include the following entries: "gmi"
16 - resets : Must contain an entry for each entry in reset-names.
[all …]
|
| D | renesas,bsc.yaml | 2 ---
4 $schema: http://devicetree.org/meta-schemas/core.yaml#
6 title: Renesas Bus State Controller (BSC)
9 - Geert Uytterhoeven <geert+renesas@glider.be>
12 The Renesas Bus State Controller (BSC, sometimes called "LBSC within Bus
13 Bridge", or "External Bus Interface") can be found in several Renesas ARM
14 SoCs. It provides an external bus for connecting multiple external
18 While the BSC is a fairly simple memory-mapped bus, it may be part of a
24 The bindings for the BSC extend the bindings for "simple-pm-bus".
27 - $ref: simple-pm-bus.yaml#
[all …]
|
| D | qcom,ebi2.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm External Bus Interface 2 (EBI2)
11 external memory (such as NAND or other memory-mapped peripherals) whereas
14 As it says it connects devices to an external bus interface, meaning address
15 lines (up to 9 address lines so can only address 1KiB external memory space),
25 Also CS1 and CS2 has -A and -B signals. Why they have that is unclear to me.
27 The chip selects have the following memory range assignments. This region of
28 memory is referred to as "Chip Peripheral SS FPB0" and is 168MB big.
[all …]
|
| /Documentation/devicetree/bindings/mfd/ |
| D | atmel-smc.txt | 1 * Device tree bindings for Atmel SMC (Static Memory Controller)
3 The SMC registers are used to configure Atmel EBI (External Bus Interface)
4 to interface with standard memory devices (NAND, NOR, SRAM or specialized
8 - compatible: Should be one of the following
9 "atmel,at91sam9260-smc", "syscon"
10 "atmel,sama5d3-smc", "syscon"
11 "atmel,sama5d2-smc", "syscon"
12 "microchip,sam9x60-smc", "syscon"
13 "microchip,sam9x7-smc", "atmel,at91sam9260-smc", "syscon"
14 - reg: Contains offset/length value of the SMC memory
[all …]
|
| /Documentation/devicetree/bindings/gpio/ |
| D | gpio-mm-lantiq.txt | 1 Lantiq SoC External Bus memory mapped GPIO controller
4 only gpios. This driver configures a special memory address, which when
7 The node describing the memory mapped GPIOs needs to be a child of the node
11 - compatible : Should be "lantiq,gpio-mm-lantiq"
12 - reg : Address and length of the register set for the device
13 - #gpio-cells : Should be two. The first cell is the pin number and
16 - gpio-controller : Marks the device node as a gpio controller.
19 - lantiq,shadow : The default value that we shall assume as already set on the
25 #address-cells = <2>;
26 #size-cells = <1>;
[all …]
|
| /Documentation/devicetree/bindings/sound/ |
| D | mediatek,mt8188-afe.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/sound/mediatek,mt8188-afe.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: MediaTek AFE PCM controller for mt8188
10 - Trevor Wu <trevor.wu@mediatek.com>
14 const: mediatek,mt8188-afe
25 reset-names:
28 memory-region:
31 Shared memory region for AFE memif. A "shared-dma-pool".
[all …]
|
| D | mvebu-audio.txt | 1 * mvebu (Kirkwood, Dove, Armada 370) audio controller
5 - compatible:
6 "marvell,kirkwood-audio" for Kirkwood platforms
7 "marvell,dove-audio" for Dove platforms
8 "marvell,armada370-audio" for Armada 370 platforms
9 "marvell,armada-380-audio" for Armada 38x platforms
11 - reg: physical base address of the controller and length of memory mapped
13 With "marvell,armada-380-audio" two other regions are required:
15 (named "pll_regs") and the second one ("soc_ctrl") - for register
18 - interrupts:
[all …]
|
| D | mt8195-afe-pcm.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/sound/mt8195-afe-pcm.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Mediatek AFE PCM controller for mt8195
10 - Trevor Wu <trevor.wu@mediatek.com>
14 const: mediatek,mt8195-audio
25 reset-names:
28 memory-region:
31 Shared memory region for AFE memif. A "shared-dma-pool".
[all …]
|
| /Documentation/arch/arm/stm32/ |
| D | stm32f429-overview.rst | 6 ------------
8 The STM32F429 is a Cortex-M4 MCU aimed at various applications.
11 - ARM Cortex-M4 up to 180MHz with FPU
12 - 2MB internal Flash Memory
13 - External memory support through FMC controller (PSRAM, SDRAM, NOR, NAND)
14 - I2C, SPI, SAI, CAN, USB OTG, Ethernet controllers
15 - LCD controller & Camera interface
16 - Cryptographic processor
19 ---------
23 …www.st.com/web/en/catalog/mmc/FM141/SC1169/SS1577/LN1806?ecmp=stm32f429-439_pron_pr-ces2014_nov2013
|
| /Documentation/arch/xtensa/ |
| D | atomctl.rst | 9 1. With and without an Coherent Cache Controller which
10 can do Atomic Transactions to the memory internally.
12 2. With and without An Intelligent Memory Controller which
19 On the FPGA Cards we typically simulate an Intelligent Memory controller
20 which can implement RCW transactions. For FPGA cards with an External
21 Memory controller we let it to the atomic operations internally while
22 doing a Cached (WB) transaction and use the Memory RCW for un-cached
25 For systems without an coherent cache controller, non-MX, we always
26 use the memory controllers RCW, though non-MX controllers likely
29 CUSTOMER-WARNING:
[all …]
|
| /Documentation/devicetree/bindings/remoteproc/ |
| D | ti,davinci-rproc.txt | 4 The TI Davinci family of SoCs usually contains a TI DSP Core sub-system that
5 is used to offload some of the processor-intensive tasks or algorithms, for
8 The processor cores in the sub-system usually contain additional sub-modules
9 like L1 and/or L2 caches/SRAMs, an Interrupt Controller, an external memory
10 controller, a dedicated local power/sleep controller etc. The DSP processor
15 Each DSP Core sub-system is represented as a single DT node.
18 --------------------
21 - compatible: Should be one of the following,
22 "ti,da850-dsp" for DSPs on OMAP-L138 SoCs
24 - reg: Should contain an entry for each value in 'reg-names'.
[all …]
|
| /Documentation/devicetree/bindings/memory-controllers/ti/ |
| D | emif.txt | 3 EMIF - External Memory Interface - is an SDRAM controller used in
6 of the EMIF IP and memory parts attached to it. Certain revisions
7 of the EMIF controller also contain optional ECC support, which
11 - compatible : Should be of the form "ti,emif-<ip-rev>" where <ip-rev>
14 "ti,emif-am3352"
15 "ti,emif-am4372"
16 "ti,emif-dra7xx"
17 "ti,emif-keystone"
19 - phy-type : <u32> indicating the DDR phy type. Following are the
24 - device-handle : phandle to a "lpddr2" node representing the memory part
[all …]
|
| /Documentation/devicetree/bindings/usb/ |
| D | lpc32xx-udc.txt | 1 * NXP LPC32xx SoC USB Device Controller (UDC)
4 - compatible: Must be "nxp,lpc3220-udc"
5 - reg: Physical base address of the controller and length of memory mapped
7 - interrupts: The USB interrupts:
11 * External USB Transceiver Interrupt (OTG ATX)
12 - transceiver: phandle of the associated ISP1301 device - this is necessary for
13 the UDC controller for connecting to the USB physical layer
17 isp1301: usb-transceiver@2c {
23 compatible = "nxp,lpc3220-udc";
25 interrupt-parent = <&mic>;
|
123456