Searched full:fifo (Results 1 – 25 of 208) sorted by relevance
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| /Documentation/devicetree/bindings/powerpc/fsl/ |
| D | mpc5121-psc.txt | 8 fsl,mpc5121-immr SoC node. Additionally the PSC FIFO
9 Controller node fsl,mpc5121-psc-fifo is required there:
19 PSC FIFO Controller and b is a field that represents an
23 - fsl,rx-fifo-size : the size of the RX fifo slice (a multiple of 4)
24 - fsl,tx-fifo-size : the size of the TX fifo slice (a multiple of 4)
30 for that is fsl,mpc5121-psc-spi. It requires a fsl,mpc5121-psc-fifo as well.
35 fsl,mpc512x-psc-fifo node
39 - compatible : Should be "fsl,<soc>-psc-fifo"
42 FIFO Controller
44 PSC FIFO Controller and b is a field that represents an
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| /Documentation/devicetree/bindings/net/can/ |
| D | xilinx,can.yaml | 37 tx-fifo-depth:
39 description: CAN Tx fifo depth (Zynq, Axi CAN).
41 rx-fifo-depth:
43 description: CAN Rx fifo depth (Zynq, Axi CAN, CAN FD in sequential Rx mode)
81 - tx-fifo-depth
82 - rx-fifo-depth
98 - tx-fifo-depth
99 - rx-fifo-depth
117 - rx-fifo-depth
130 tx-fifo-depth = <0x40>;
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| D | bosch,m_can.yaml | 57 and each element(e.g Rx FIFO or Tx Buffer and etc) number
67 are used to specify how many elements are used for each FIFO/Buffer.
72 Rx FIFO 0 0-64 elements / 0-1152 words
73 Rx FIFO 1 0-64 elements / 0-1152 words
75 Tx Event FIFO 0-32 elements / 0-64 words
92 - description: Rx FIFO 0 0-64 elements / 0-1152 words
95 - description: Rx FIFO 1 0-64 elements / 0-1152 words
101 - description: Tx Event FIFO 0-32 elements / 0-64 words
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| /Documentation/devicetree/bindings/mmc/ |
| D | synopsys-dw-mshc-common.yaml | 29 fifo-depth:
31 The maximum size of the tx/rx fifo's. If this property is not
32 specified, the default value of the fifo size is determined from the
45 Override fifo address with value provided by DT. The default FIFO reg
48 this property to set fifo address in device tree.
51 fifo-watermark-aligned:
54 watermark in PIO mode. But fifo watermark is requested to be aligned
57 force fifo watermark setting accordingly.
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| /Documentation/devicetree/bindings/interrupt-controller/ |
| D | cirrus,clps711x-intc.txt | 24 12: UTXINT1 UART1 transmit FIFO half empty
25 13: URXINT1 UART1 receive FIFO half full
29 17: SS2RX SSI2 receive FIFO half or greater full
30 18: SS2TX SSI2 transmit FIFO less than half empty
31 28: UTXINT2 UART2 transmit FIFO half empty
32 29: URXINT2 UART2 receive FIFO half full
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| /Documentation/devicetree/bindings/spi/ |
| D | spi-controller.yaml | 72 fifo-depth:
77 rx-fifo-depth:
80 Size of the RX data FIFO in bytes.
82 tx-fifo-depth:
85 Size of the TX data FIFO in bytes.
135 rx-fifo-depth: [ tx-fifo-depth ]
136 tx-fifo-depth: [ rx-fifo-depth ]
153 - fifo-depth
154 - rx-fifo-depth
157 - fifo-depth
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| D | cdns,qspi-nor.yaml | 56 cdns,fifo-depth:
61 cdns,fifo-depth:
102 cdns,fifo-depth:
104 Size of the data FIFO in words.
107 cdns,fifo-width:
110 Bus width of the data FIFO in bytes.
149 - cdns,fifo-width
166 cdns,fifo-depth = <128>;
167 cdns,fifo-width = <4>;
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| /Documentation/devicetree/bindings/net/ |
| D | altr,tse.yaml | 28 rx-fifo-depth:
31 Depth in bytes of the RX FIFO
33 tx-fifo-depth:
36 Depth in bytes of the TX FIFO
65 - rx-fifo-depth
66 - tx-fifo-depth
127 rx-fifo-depth = <2048>;
128 tx-fifo-depth = <2048>;
150 rx-fifo-depth = <2048>;
151 tx-fifo-depth = <2048>;
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| D | ibm,emac.txt | 32 - rx-fifo-size : 1 cell, Rx fifo size in bytes for 10 and 100 Mb/sec
35 - tx-fifo-size : 1 cell, Tx fifo size in bytes for 10 and 100 Mb/sec
38 - fifo-entry-size : 1 cell, size of a fifo entry (used to calculate
76 - rx-fifo-size-gige : 1 cell, Rx fifo size in bytes for 1000 Mb/sec
78 rx-fifo-size). For Axon, either absent or 2048.
79 - tx-fifo-size-gige : 1 cell, Tx fifo size in bytes for 1000 Mb/sec
81 tx-fifo-size). For Axon, either absent or 2048.
115 rx-fifo-size = <1000>;
116 tx-fifo-size = <800>;
140 rx-fifo-size = <16384>;
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| D | ti,dp83867.yaml | 61 tx-fifo-depth:
64 Transmitt FIFO depth see dt-bindings/net/ti-dp83867.h for values
66 rx-fifo-depth:
69 Receive FIFO depth see dt-bindings/net/ti-dp83867.h for values
114 ti,fifo-depth:
118 Transmitt FIFO depth- see dt-bindings/net/ti-dp83867.h for applicable
134 tx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
135 rx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
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| D | ti,dp83869.yaml | 46 tx-fifo-depth:
49 Transmitt FIFO depth see dt-bindings/net/ti-dp83869.h for values
51 rx-fifo-depth:
54 Receive FIFO depth see dt-bindings/net/ti-dp83869.h for values
92 tx-fifo-depth = <DP83869_PHYCR_FIFO_DEPTH_4_B_NIB>;
93 rx-fifo-depth = <DP83869_PHYCR_FIFO_DEPTH_4_B_NIB>;
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| /Documentation/networking/device_drivers/can/freescale/ |
| D | flexcan.rst | 15 - FIFO
20 configured for RX-FIFO mode.
22 The RX FIFO mode uses a hardware FIFO with a depth of 6 CAN frames,
23 while the mailbox mode uses a software FIFO with a depth of up to 62
40 more performant "RX mailbox" mode and will use "RX FIFO" mode
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| /Documentation/devicetree/bindings/pinctrl/ |
| D | cirrus,madera.yaml | 72 timer7-sts, timer8-sts, log1-fifo-ne,
73 log2-fifo-ne, log3-fifo-ne, log4-fifo-ne,
74 log5-fifo-ne, log6-fifo-ne, log7-fifo-ne,
75 log8-fifo-ne ]
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| /Documentation/devicetree/bindings/display/bridge/ |
| D | sil,sii9022.yaml | 63 Each integer indicates which I2S pin is connected to which audio FIFO.
64 The first integer selects the I2S audio pin for the first audio FIFO#0
65 (HDMI channels 1&2), the second for FIFO#1 (HDMI channels 3&4), and so
67 connected to any FIFO, but there can be no gaps. E.g. an I2S pin must be
68 mapped to FIFO#0 and FIFO#1 before mapping a channel to FIFO#2. The
70 FIFO#0.
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| /Documentation/devicetree/bindings/sound/ |
| D | amlogic,axg-fifo.yaml | 4 $id: http://devicetree.org/schemas/sound/amlogic,axg-fifo.yaml#
7 title: Amlogic AXG Audio FIFO controllers
50 amlogic,fifo-depth:
52 description: Size of the controller's fifo in bytes
61 - amlogic,fifo-depth
111 amlogic,fifo-depth = <512>;
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| /Documentation/devicetree/bindings/dma/stm32/ |
| D | st,stm32-dma.yaml | 34 -bit 0-1: DMA FIFO threshold selection
35 0x0: 1/4 full FIFO
36 0x1: 1/2 full FIFO
37 0x2: 3/4 full FIFO
38 0x3: full FIFO
40 0x0: FIFO mode with threshold selectable with bit 0-1
42 from/to the memory, FIFO is bypassed.
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| D | st,stm32-dma3.yaml | 66 -bit 4-7: The FIFO requirement for queuing source/destination transfers
67 0x0: no FIFO requirement/any channel can fit
68 0x2: FIFO of 8 bytes (2^2+1)
69 0x4: FIFO of 32 bytes (2^4+1)
70 0x6: FIFO of 128 bytes (2^6+1)
71 0x7: FIFO of 256 bytes (2^7+1)
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| /Documentation/devicetree/bindings/mailbox/ |
| D | apple,mailbox.yaml | 18 FIFO is used for the other direction.
52 - description: send fifo is empty interrupt
53 - description: send fifo is not empty interrupt
54 - description: receive fifo is empty interrupt
55 - description: receive fifo is not empty interrupt
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| D | arm,mhuv3.yaml | 83 - FIFO Extension (FE): FE defines a Channel type called a FIFO Channel (FFCH).
87 FIFO has room for the Transfer.
98 memory region, wherein the MHU FIFO is used to transmit, in order, a small
142 description: PBX/MBX FIFO Combined interrupt
144 description: PBX/MBX FIFO Channel <N> Low Tide interrupt
146 description: PBX/MBX FIFO Channel <N> High Tide interrupt
148 description: PBX/MBX FIFO Channel <N> Flush interrupt
156 description: MBX FIFO Channel <N> Transfer interrupt
160 description: PBX FIFO Channel <N> Transfer Ack interrupt
179 mboxes = <&mhu FE_EXT 1 0>; // FE, FIFO Channel Window 1.
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| /Documentation/accel/qaic/ |
| D | aic100.rst | 246 FIFO is the request FIFO. The other FIFO is the response FIFO.
250 * Request FIFO head pointer (offset 0x0). Read only by the host. Indicates the
251 latest item in the FIFO the device has consumed.
252 * Request FIFO tail pointer (offset 0x4). Read/write by the host. Host
253 increments this register to add new items to the FIFO.
254 * Response FIFO head pointer (offset 0x8). Read/write by the host. Indicates
255 the latest item in the FIFO the host has consumed.
256 * Response FIFO tail pointer (offset 0xc). Read only by the host. Device
257 increments this register to add new items to the FIFO.
259 The values in each register are indexes in the FIFO. To get the location of the
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| /Documentation/security/tpm/ |
| D | tpm_tis.rst | 4 TPM FIFO interface driver
7 TCG PTP Specification defines two interface types: FIFO and CRB. The former is
11 FIFO (First-In-First-Out) interface is used by the tpm_tis_core dependent
17 framework for FIFO drivers is named as tpm_tis_core. The postfix "tis" in
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| /Documentation/devicetree/bindings/display/mediatek/ |
| D | mediatek,rdma.yaml | 71 mediatek,rdma-fifo-size:
73 rdma fifo size may be different even in same SOC, add this property to the
76 mediatek,rdma-fifo-size of mt8173-rdma0 is 8K
77 mediatek,rdma-fifo-size of mt8183-rdma0 is 5K
78 mediatek,rdma-fifo-size of mt8183-rdma1 is 2K
119 mediatek,rdma-fifo-size = <8192>;
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| /Documentation/devicetree/bindings/net/ieee802154/ |
| D | cc2520.txt | 10 - fifo-gpio: GPIO spec for the FIFO pin
27 fifo-gpio = <&gpio1 18 0>;
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| /Documentation/devicetree/bindings/display/tilcdc/ |
| D | panel.txt | 10 - fdd: FIFO DMA Request Delay
14 - fifo-th: DMA FIFO threshold
48 fifo-th = <0>;
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| /Documentation/devicetree/bindings/serial/ |
| D | mvebu-uart.txt | 7 (32 bytes FIFO, no DMA, level interrupts, 8-bit access to the
8 FIFO), called also UART1.
10 UART (128 bytes FIFO, DMA, front interrupts, 8-bit or 32-bit
11 accesses to the FIFO), called also UART2.
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