Searched +full:fixed +full:- +full:length (Results 1 – 25 of 144) sorted by relevance
123456
| /Documentation/devicetree/bindings/net/ |
| D | samsung-sxgbe.txt | 4 - compatible: Should be "samsung,sxgbe-v2.0a"
5 - reg: Address and length of the register set for the device
6 - interrupts: Should contain the SXGBE interrupts
7 These interrupts are ordered by fixed and follows variable
9 index 0 - this is fixed common interrupt of SXGBE and it is always
11 index 1 to 25 - 8 variable transmit interrupts, variable 16 receive interrupts
13 - phy-mode: String, operation mode of the PHY interface.
15 - samsung,pbl: Integer, Programmable Burst Length.
17 - samsung,burst-map: Integer, Program the possible bursts supported by sxgbe
18 This is an integer and represents allowable DMA bursts when fixed burst.
[all …]
|
| D | fsl-tsec-phy.txt | 5 the definition of the PHY node in booting-without-of.txt for an example
9 - reg : Offset and length of the register set for the device, and optionally
10 the offset and length of the TBIPA register (TBI PHY address
14 - compatible : Should define the compatible device type for the
16 - "fsl,gianfar-tbi"
17 - "fsl,gianfar-mdio"
18 - "fsl,etsec2-tbi"
19 - "fsl,etsec2-mdio"
20 - "fsl,ucc-mdio"
21 - "fsl,fman-mdio"
[all …]
|
| D | qcom,ipq4019-mdio.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/net/qcom,ipq4019-mdio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Robert Marko <robert.marko@sartura.hr>
15 - enum:
16 - qcom,ipq4019-mdio
17 - qcom,ipq5018-mdio
19 - items:
20 - enum:
[all …]
|
| D | nixge.txt | 4 - compatible: Should be "ni,xge-enet-3.00", but can be "ni,xge-enet-2.00" for
5 older device trees with DMA engines co-located in the address map,
7 - reg: Address and length of the register set for the device. It contains the
8 information of registers in the same order as described by reg-names.
9 - reg-names: Should contain the reg names
12 - interrupts: Should contain tx and rx interrupt
13 - interrupt-names: Should be "rx" and "tx"
14 - phy-mode: See ethernet.txt file in the same directory.
15 - nvmem-cells: Phandle of nvmem cell containing the MAC address
16 - nvmem-cell-names: Should be "address"
[all …]
|
| /Documentation/devicetree/bindings/nvmem/layouts/ |
| D | fixed-cell.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/nvmem/layouts/fixed-cell.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Fixed offset & size NVMEM cell
10 - Rafał Miłecki <rafal@milecki.pl>
11 - Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
16 - const: mac-base
20 It can be stored in a plain binary format (cell length 6) or as an
21 ASCII text like "00:11:22:33:44:55" (cell length 17).
[all …]
|
| D | nvmem-layout.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/nvmem/layouts/nvmem-layout.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
11 - Michael Walle <michael@walle.cc>
12 - Miquel Raynal <miquel.raynal@bootlin.com>
16 besides the bytes/bits offset and length. Other layouts can be less statically
18 perform their parsing. The nvmem-layout container is here to describe these.
21 - $ref: fixed-layout.yaml
[all …]
|
| /Documentation/devicetree/bindings/clock/ |
| D | nuvoton,npcm750-clk.txt | 8 There are six fixed clocks that are generated outside the BMC. All clocks are of
9 a known fixed value that cannot be changed. clk_refclk, clk_mcbypck and
17 dt-bindings/clock/nuvoton,npcm7xx-clock.h
22 - compatible: "nuvoton,npcm750-clk" : for clock controller of Nuvoton
25 - reg: physical base address of the clock controller and length of
28 - #clock-cells: should be 1.
32 clk: clock-controller@f0801000 {
33 compatible = "nuvoton,npcm750-clk";
34 #clock-cells = <1>;
36 clock-names = "refclk", "sysbypck", "mcbypck";
[all …]
|
| D | axs10x-i2s-pll-clock.txt | 5 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
8 - compatible: shall be "snps,axs10x-i2s-pll-clock"
9 - reg : address and length of the I2S PLL register set.
10 - clocks: shall be the input parent clock phandle for the PLL.
11 - #clock-cells: from common clock binding; Should always be set to 0.
15 compatible = "fixed-clock";
16 clock-frequency = <27000000>;
17 #clock-cells = <0>;
21 compatible = "snps,axs10x-i2s-pll-clock";
24 #clock-cells = <0>;
|
| D | snps,hsdk-pll-clock.txt | 5 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
8 - compatible: should be "snps,hsdk-<name>-pll-clock"
9 "snps,hsdk-core-pll-clock"
10 "snps,hsdk-gp-pll-clock"
11 "snps,hsdk-hdmi-pll-clock"
12 - reg : should contain base register location and length.
13 - clocks: shall be the input parent clock phandle for the PLL.
14 - #clock-cells: from common clock binding; Should always be set to 0.
17 input_clk: input-clk {
18 clock-frequency = <33333333>;
[all …]
|
| D | snps,pll-clock.txt | 5 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
8 - compatible: should be "snps,axs10x-<name>-pll-clock"
9 "snps,axs10x-arc-pll-clock"
10 "snps,axs10x-pgu-pll-clock"
11 - reg: should always contain 2 pairs address - length: first for PLL config
13 - clocks: shall be the input parent clock phandle for the PLL.
14 - #clock-cells: from common clock binding; Should always be set to 0.
17 input-clk: input-clk {
18 clock-frequency = <33333333>;
19 compatible = "fixed-clock";
[all …]
|
| D | artpec6.txt | 1 * Clock bindings for Axis ARTPEC-6 chip
4 Documentation/devicetree/bindings/clock/clock-bindings.txt
7 ----------------
11 - "sys_refclk": External 50 Mhz oscillator (required)
12 - "i2s_refclk": Alternate audio reference clock (optional).
15 ---------------------
18 - #clock-cells: Should be <1>
19 See dt-bindings/clock/axis,artpec6-clkctrl.h for the list of valid identifiers.
20 - compatible: Should be "axis,artpec6-clkctrl"
21 - reg: Must contain the base address and length of the system controller
[all …]
|
| /Documentation/devicetree/bindings/sound/ |
| D | brcm,bcm63xx-audio.txt | 4 - compatible: Should be "brcm,bcm63xx-i2s".
5 - #address-cells: 32bit valued, 1 cell.
6 - #size-cells: 32bit valued, 0 cell.
7 - reg: Should contain audio registers location and length
8 - interrupts: Should contain the interrupt for the controller.
9 - clocks: Must contain an entry for each entry in clock-names.
10 Please refer to clock-bindings.txt.
11 - clock-names: One of each entry matching the clocks phandles list:
12 - "i2sclk" (generated clock) Required.
13 - "i2sosc" (fixed 200MHz clock) Required.
[all …]
|
| /Documentation/devicetree/bindings/timer/ |
| D | marvell,armada-370-xp-timer.txt | 2 ---------------------------------------
5 - compatible: Should be one of the following
6 "marvell,armada-370-timer",
7 "marvell,armada-375-timer",
8 "marvell,armada-xp-timer".
9 - interrupts: Should contain the list of Global Timer interrupts and
11 - reg: Should contain location and length for timers register. First
15 Clocks required for compatible = "marvell,armada-370-timer":
16 - clocks : Must contain a single entry describing the clock input
18 Clocks required for compatibles = "marvell,armada-xp-timer",
[all …]
|
| /Documentation/devicetree/bindings/dma/ |
| D | mpc512x-dma.txt | 11 - compatible: should be "fsl,mpc5121-dma" or "fsl,mpc8308-dma";
12 - reg: should contain the DMA controller registers location and length;
13 - interrupt for the DMA controller: syntax of interrupt client node
14 is described in interrupt-controller/interrupts.txt file.
15 - #dma-cells: the length of the DMA specifier, must be <1>.
17 the assignment is fixed in hardware. This one cell
23 compatible = "fsl,mpc5121-dma";
26 #dma-cells = <1>;
|
| /Documentation/networking/ |
| D | radiotap-headers.rst | 1 .. SPDX-License-Identifier: GPL-2.0
8 ------------------------------------
10 Radiotap headers are variable-length and extensible, you can get most of the
19 -----------------------
21 There is a fixed portion at the start which contains a u32 bitmap that defines
29 < 8-byte ieee80211_radiotap_header >
44 --------------------------
46 After the fixed part of the header, the arguments follow for each argument
50 - the arguments are all stored little-endian!
52 - the argument payload for a given argument index has a fixed size. So
[all …]
|
| /Documentation/fb/ |
| D | api.rst | 9 ---------------
12 with frame buffer devices. In-kernel APIs between device drivers and the frame
22 ---------------
24 Device and driver capabilities are reported in the fixed screen information
36 - FB_CAP_FOURCC
44 --------------------
46 Pixels are stored in memory in hardware-dependent formats. Applications need
58 - FB_TYPE_PACKED_PIXELS
64 Padding at end of lines may be present and is then reported through the fixed
67 - FB_TYPE_PLANES
[all …]
|
| /Documentation/devicetree/bindings/rtc/ |
| D | xgene-rtc.txt | 1 * APM X-Gene Real Time Clock
3 RTC controller for the APM X-Gene Real Time Clock
6 - compatible : Should be "apm,xgene-rtc"
7 - reg: physical base address of the controller and length of memory mapped
9 - interrupts: IRQ line for the RTC.
10 - #clock-cells: Should be 1.
11 - clocks: Reference to the clock entry.
16 compatible = "fixed-clock";
17 #clock-cells = <1>;
18 clock-frequency = <100000000>;
[all …]
|
| /Documentation/ABI/testing/ |
| D | sysfs-bus-mei | 5 linux-mei@linux.intel.com
21 Format: xxxxxxxx-xxxx-xxxx-xxxx-xxxxxxxxxxxx
37 What: /sys/bus/mei/devices/.../fixed
41 Description: Stores mei client fixed address, if any
55 Description: Stores mei client maximum message length
|
| /Documentation/netlink/ |
| D | genetlink-legacy.yaml | 1 # SPDX-License-Identifier: ((GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause)
3 ---
4 $id: http://kernel.org/schemas/netlink/genetlink-legacy.yaml#
5 $schema: https://json-schema.org/draft-07/schema
12 len-or-define:
14 pattern: ^[0-9A-Za-z_-]+( - 1)?$
16 len-or-limit:
17 # literal int or limit based on fixed-width type e.g. u8-min, u16-max, etc.
19 pattern: ^[su](8|16|32|64)-(min|max)$
26 required: [ name, doc, attribute-sets, operations ]
[all …]
|
| D | netlink-raw.yaml | 1 # SPDX-License-Identifier: ((GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause)
3 ---
4 $id: http://kernel.org/schemas/netlink/netlink-raw.yaml#
5 $schema: https://json-schema.org/draft-07/schema
12 len-or-define:
14 pattern: ^[0-9A-Za-z_-]+( - 1)?$
21 required: [ name, doc, attribute-sets, operations ]
31 enum: [ netlink-raw ] # Trim
32 # Start netlink-raw
34 description: Protocol number to use for netlink-raw
[all …]
|
| /Documentation/devicetree/bindings/mtd/ |
| D | samsung-s3c2410.txt | 4 - compatible : The possible values are:
5 "samsung,s3c2410-nand"
6 "samsung,s3c2412-nand"
7 "samsung,s3c2440-nand"
8 - reg : register's location and length.
9 - #address-cells, #size-cells : see nand-controller.yaml
10 - clocks : phandle to the nand controller clock
11 - clock-names : must contain "nand"
17 - nand-ecc-mode : see nand-controller.yaml
18 - nand-on-flash-bbt : see nand-controller.yaml
[all …]
|
| /Documentation/devicetree/bindings/gpio/ |
| D | gpio-altera.txt | 4 - compatible:
5 - "altr,pio-1.0"
6 - reg: Physical base address and length of the controller's registers.
7 - #gpio-cells : Should be 2
8 - The first cell is the gpio offset number.
9 - The second cell is reserved and is currently unused.
10 - gpio-controller : Marks the device node as a GPIO controller.
11 - interrupt-controller: Mark the device node as an interrupt controller
12 - #interrupt-cells : Should be 2. The interrupt type is fixed in the hardware.
13 - The first cell is the GPIO offset number within the GPIO controller.
[all …]
|
| /Documentation/arch/sparc/oradax/ |
| D | dax-hv-api.txt | 3 Publication date 2017-09-25 08:21
5 Extracted via "pdftotext -f 547 -l 572 -layout sun4v_20170925.pdf"
16 live-migration and other system management activities.
20 …high speed processoring of database-centric operations. The coprocessors may support one or more of
28 …e Completion Area and, unless execution order is specifically restricted through the use of serial-
38 …There is no fixed limit on the number of outstanding CCBs guest software may have queued in the vi…
45 …device node in the guest MD (Section 8.24.17, “Database Analytics Accelerators (DAX) virtual-device
51 36.1.1.1. "ORCL,sun4v-dax" Device Compatibility
54 • No-op/Sync
81 36.1.1.2. "ORCL,sun4v-dax-fc" Device Compatibility
[all …]
|
| /Documentation/security/keys/ |
| D | trusted-encrypted.rst | 6 key ring service. Both of these new types are variable length symmetric keys,
33 (2) TEE (Trusted Execution Environment: OP-TEE based on Arm TrustZone)
35 Rooted to Hardware Unique Key (HUK) which is generally burnt in on-chip
41 mode, trust is rooted to the OTPMK, a never-disclosed 256-bit key
43 Otherwise, a common fixed test key is used instead.
45 (4) DCP (Data Co-Processor: crypto accelerator of various i.MX SoCs)
47 Rooted to a one-time programmable key (OTP) that is generally burnt
48 in the on-chip fuses and is accessible to the DCP encryption engine only.
57 Fixed set of operations running in isolated execution environment.
66 Fixed set of operations running in isolated execution environment.
[all …]
|
| /Documentation/devicetree/bindings/pwm/ |
| D | pwm-st.txt | 2 --------------------------------------
5 - compatible : "st,pwm"
6 - #pwm-cells : Number of cells used to specify a PWM. First cell
7 specifies the per-chip index of the PWM to use and the
8 second cell is the period in nanoseconds - fixed to 2
10 - reg : Physical base address and length of the controller's
12 - pinctrl-names: Set to "default".
13 - pinctrl-0: List of phandles pointing to pin configuration nodes
16 - clock-names: Valid entries are "pwm" and/or "capture".
17 - clocks: phandle of the clock used by the PWM module.
[all …]
|
123456