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/Documentation/devicetree/bindings/net/
Dnixge.txt4 - compatible: Should be "ni,xge-enet-3.00", but can be "ni,xge-enet-2.00" for
5 older device trees with DMA engines co-located in the address map,
7 - reg: Address and length of the register set for the device. It contains the
8 information of registers in the same order as described by reg-names.
9 - reg-names: Should contain the reg names
12 - interrupts: Should contain tx and rx interrupt
13 - interrupt-names: Should be "rx" and "tx"
14 - phy-mode: See ethernet.txt file in the same directory.
15 - nvmem-cells: Phandle of nvmem cell containing the MAC address
16 - nvmem-cell-names: Should be "address"
[all …]
Dethernet-controller.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/net/ethernet-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - David S. Miller <davem@davemloft.net>
19 local-mac-address:
22 $ref: /schemas/types.yaml#/definitions/uint8-array
26 mac-address:
31 local-mac-address property.
32 $ref: /schemas/types.yaml#/definitions/uint8-array
[all …]
Dcpsw.txt2 ------------------------------------------------------
5 - compatible : Should be one of the below:-
7 "ti,am335x-cpsw" for AM335x controllers
8 "ti,am4372-cpsw" for AM437x controllers
9 "ti,dra7-cpsw" for DRA7x controllers
10 - reg : physical base address and size of the cpsw
12 - interrupts : property with a value describing the interrupt
14 - cpdma_channels : Specifies number of channels in CPDMA
15 - ale_entries : Specifies No of entries ALE can hold
16 - bd_ram_size : Specifies internal descriptor RAM size
[all …]
Dti,dp83822.yaml1 # SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Andrew Davis <afd@ti.com>
14 The DP83822 is a low-power, single-port, 10/100 Mbps Ethernet PHY. It
16 data over standard, twisted-pair cables or to connect to an external,
17 fiber-optic transceiver. Additionally, the DP83822 provides flexibility to
24 - $ref: ethernet-phy.yaml#
30 ti,link-loss-low:
34 Sets the DP83822 to detect a link drop condition when the signal goes
[all …]
Dfsl-tsec-phy.txt5 the definition of the PHY node in booting-without-of.txt for an example
9 - reg : Offset and length of the register set for the device, and optionally
14 - compatible : Should define the compatible device type for the
16 - "fsl,gianfar-tbi"
17 - "fsl,gianfar-mdio"
18 - "fsl,etsec2-tbi"
19 - "fsl,etsec2-mdio"
20 - "fsl,ucc-mdio"
21 - "fsl,fman-mdio"
23 - "gianfar"
[all …]
/Documentation/devicetree/bindings/sound/
Daudio-graph-port.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/sound/audio-graph-port.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
15 port-base:
17 - $ref: /schemas/graph.yaml#/$defs/port-base
18 - $ref: /schemas/sound/dai-params.yaml#
20 mclk-fs:
21 $ref: simple-card.yaml#/definitions/mclk-fs
[all …]
Dsimple-card.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/sound/simple-card.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
14 frame-master:
15 description: Indicates dai-link frame master.
18 bitclock-master:
19 description: Indicates dai-link bit clock master
22 frame-inversion:
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/Documentation/devicetree/bindings/net/dsa/
Dlan9303.txt2 -------------------------------------------------
6 - compatible: should be
7 - "smsc,lan9303-i2c" for I2C managed mode
9 - "smsc,lan9303-mdio" for mdio managed mode
13 - reset-gpios: GPIO to be used to reset the whole device
14 - reset-duration: reset duration in milliseconds, defaults to 200 ms
23 auto-detected and mapped accordingly.
31 fixed-link { /* RMII fixed link to LAN9303 */
33 full-duplex;
38 compatible = "smsc,lan9303-i2c";
[all …]
Dmicrochip,lan937x.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - UNGLinuxDriver@microchip.com
13 - $ref: dsa.yaml#/$defs/ethernet-ports
18 - microchip,lan9370
19 - microchip,lan9371
20 - microchip,lan9372
21 - microchip,lan9373
22 - microchip,lan9374
[all …]
Dmscc,ocelot.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Vladimir Oltean <vladimir.oltean@nxp.com>
11 - Claudiu Manoil <claudiu.manoil@nxp.com>
12 - Alexandre Belloni <alexandre.belloni@bootlin.com>
13 - UNGLinuxDriver@microchip.com
16 There are multiple switches which are either part of the Ocelot-1 family, or
22 Frame DMA or register-based I/O.
26 This is found in the NXP T1040, where it is a memory-mapped platform
[all …]
Ddsa-port.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/dsa/dsa-port.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Andrew Lunn <andrew@lunn.ch>
11 - Florian Fainelli <f.fainelli@gmail.com>
12 - Vladimir Oltean <olteanv@gmail.com>
17 DSA-specific functionality.
19 $ref: /schemas/net/ethernet-switch-port.yaml#
24 - description: Port number
[all …]
Dbrcm,b53.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Florian Fainelli <f.fainelli@gmail.com>
18 - const: brcm,bcm5325
19 - const: brcm,bcm53115
20 - const: brcm,bcm53125
21 - const: brcm,bcm53128
22 - const: brcm,bcm53134
23 - const: brcm,bcm5365
[all …]
Dmicrochip,ksz.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Marek Vasut <marex@denx.de>
11 - Woojung Huh <Woojung.Huh@microchip.com>
14 - $ref: /schemas/spi/spi-peripheral-props.yaml#
21 - microchip,ksz8765
22 - microchip,ksz8794
23 - microchip,ksz8795
24 - microchip,ksz8863
[all …]
/Documentation/networking/
Dsfp-phylink.rst1 .. SPDX-License-Identifier: GPL-2.0
10 phylink is a mechanism to support hot-pluggable networking modules
11 directly connected to a MAC without needing to re-initialise the
12 adapter on hot-plug events.
14 phylink supports conventional phylib-based setups, fixed link setups
25 In PHY mode, we use phylib to read the current link settings from
28 negotiation being enabled on the link.
30 2. Fixed mode
32 Fixed mode is the same as PHY mode as far as the MAC driver is
35 3. In-band mode
[all …]
/Documentation/devicetree/bindings/media/i2c/
Dmaxim,max96714.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Maxim MAX96714 GMSL2 to CSI-2 Deserializer
11 - Julien Massot <julien.massot@collabora.com>
15 CSI-2 D-PHY formatted output. The device allows the GMSL2 link to
16 simultaneously transmit bidirectional control-channel data while forward
18 remotely located serializer using industry-standard coax or STP
23 The GMSL2 serial link operates at a fixed rate of 3Gbps or 6Gbps in the
25 MAX96714F only supports a fixed rate of 3Gbps in the forward direction.
[all …]
Dmaxim,max96717.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: MAX96717 CSI-2 to GMSL2 Serializer
11 - Julien Massot <julien.massot@collabora.com>
14 The MAX96717 serializer converts MIPI CSI-2 D-PHY formatted input
15 into GMSL2 serial outputs. The device allows the GMSL2 link to
16 simultaneously transmit bidirectional control-channel data while forward
18 remotely located deserializer using industry-standard coax or STP
25 The GMSL2 serial link operates at a fixed rate of 3Gbps or 6Gbps in the
[all …]
Dsony,imx334.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Paul J. Murphy <paul.j.murphy@intel.com>
12 - Daniele Alessandrelli <daniele.alessandrelli@intel.com>
17 I2C client address is fixed to 0x1a as per sensor data sheet. Image data is
18 sent through MIPI CSI-2.
27 assigned-clocks: true
28 assigned-clock-parents: true
29 assigned-clock-rates: true
[all …]
Dsony,imx412.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Paul J. Murphy <paul.j.murphy@intel.com>
12 - Daniele Alessandrelli <daniele.alessandrelli@intel.com>
17 I2C client address is fixed to 0x1a as per sensor data sheet. Image data is
18 sent through MIPI CSI-2.
23 - sony,imx412
24 - sony,imx577
29 assigned-clocks: true
[all …]
Dsony,imx283.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Kieran Bingham <kieran.bingham@ideasonboard.com>
12 - Umang Jain <umang.jain@ideasonboard.com>
17 I2C client address is fixed to 0x1a as per sensor data sheet. Image data is
18 sent through MIPI CSI-2.
31 vadd-supply:
34 vdd1-supply:
37 vdd2-supply:
[all …]
Dovti,ov9282.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Paul J. Murphy <paul.j.murphy@intel.com>
12 - Daniele Alessandrelli <daniele.alessandrelli@intel.com>
17 I2C interface. The I2C client address is fixed to 0x60/0x70 as per sensor data
18 sheet. Image data is sent through MIPI CSI-2.
24 - ovti,ov9281
25 - ovti,ov9282
30 assigned-clocks: true
[all …]
/Documentation/firmware-guide/acpi/dsd/
Dphy.rst1 .. SPDX-License-Identifier: GPL-2.0
14 for connecting PHYs on the MDIO bus [dsd-properties-rules] to the MAC layer.
17 Properties UUID For _DSD" [dsd-guide] document and the
18 daffd814-6eba-4d8c-8a91-bc9bbf4aa301 UUID must be used in the Device
21 phy-handle
22 ----------
23 For each MAC node, a device property "phy-handle" is used to reference
30 .. code-block:: none
48 phy-mode
49 --------
[all …]
/Documentation/block/
Dcmdline-partition.rst8 It is typically used for fixed block (eMMC) embedded devices.
15 blkdevparts=<blkdev-def>[;<blkdev-def>]
16 <blkdev-def> := <blkdev-id>:<partdef>[,<partdef>]
17 <partdef> := <size>[@<offset>](part-name)
19 <blkdev-id>
20 block device disk name. Embedded device uses fixed block device.
21 Its disk name is also fixed, such as: mmcblk0, mmcblk1, mmcblk0boot0.
29 "-" is used to denote all remaining space.
37 (part-name)
39 create a link to block device partition with the name "PARTNAME".
[all …]
/Documentation/networking/dsa/
Dsja1105.rst8 The NXP SJA1105 is a family of 10 SPI-managed automotive switches:
10 - SJA1105E: First generation, no TTEthernet
11 - SJA1105T: First generation, TTEthernet
12 - SJA1105P: Second generation, no TTEthernet, no SGMII
13 - SJA1105Q: Second generation, TTEthernet, no SGMII
14 - SJA1105R: Second generation, no TTEthernet, SGMII
15 - SJA1105S: Second generation, TTEthernet, SGMII
16 - SJA1110A: Third generation, TTEthernet, SGMII, integrated 100base-T1 and
17 100base-TX PHYs
18 - SJA1110B: Third generation, TTEthernet, SGMII, 100base-T1, 100base-TX
[all …]
/Documentation/driver-api/cxl/
Daccess-coordinates.rst1 .. SPDX-License-Identifier: GPL-2.0
8 Shared Upstream Link Calculation
12 the endpoints behind a switch being more than the switch upstream link.
16 upstream link being a limiting factor in mind.
26 a CXL Host Bridge (HB). There can be multiple HBs under a CXL Fixed Memory
35 > ACPI0017-0 ACPI0017-1
36 > GP0/HB0/ACPI0016-0 GP1/HB1/ACPI0016-1
47 Min(SW 0 Upstream Link to RP0 BW,
48 Min(SW0SSLBIS for SW0DSP0 (EP0), EP0 DSLBIS, EP0 Upstream Link) +
49 Min(SW0SSLBIS for SW0DSP1 (EP1), EP1 DSLBIS, EP1 Upstream link)) +
[all …]
/Documentation/networking/device_drivers/ethernet/amd/
Dpds_core.rst1 .. SPDX-License-Identifier: GPL-2.0+
15 # lspci -d 1dd8:100c
24 pds_core 0000:b5:00.0: 252.048 Gb/s available PCIe bandwidth (16.0 GT/s PCIe x16 link)
25 pds_core 0000:b5:00.0: FW: 1.60.0-73
26 pds_core 0000:b6:00.0: 252.048 Gb/s available PCIe bandwidth (16.0 GT/s PCIe x16 link)
27 pds_core 0000:b6:00.0: FW: 1.60.0-73
36 fixed:
40 fw 1.51.0-73
42 fw.goldfw 1.15.9-C-22
43 fw.mainfwa 1.60.0-73
[all …]

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