Searched +full:fixed +full:- +full:rate (Results 1 – 25 of 112) sorted by relevance
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| /Documentation/devicetree/bindings/clock/ |
| D | fixed-mmio-clock.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/clock/fixed-mmio-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Simple memory mapped IO fixed-rate clock sources
10 This binding describes a fixed-rate clock for which the frequency can
11 be read from a single 32-bit memory mapped I/O register.
17 - Jan Kotas <jank@cadence.com>
21 const: fixed-mmio-clock
26 "#clock-cells":
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| D | fixed-factor-clock.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/clock/fixed-factor-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Simple fixed factor rate clock sources
10 - Michael Turquette <mturquette@baylibre.com>
11 - Stephen Boyd <sboyd@kernel.org>
16 - description:
17 If the frequency is fixed, the preferred name is 'clock-<freq>' with
19 pattern: "^clock-([0-9]+|[0-9a-z-]+)$"
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| D | fixed-clock.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/clock/fixed-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Simple fixed-rate clock sources
10 - Michael Turquette <mturquette@baylibre.com>
11 - Stephen Boyd <sboyd@kernel.org>
16 - description:
17 Preferred name is 'clock-<freq>' with <freq> being the output
18 frequency as defined in the 'clock-frequency' property.
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| D | canaan,k210-clk.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/canaan,k210-clk.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Damien Le Moal <dlemoal@kernel.org>
18 - dt-bindings/clock/k210-clk.h
22 const: canaan,k210-clk
27 Phandle of the SoC 26MHz fixed-rate oscillator clock.
29 '#clock-cells':
33 - compatible
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| D | samsung,s5pv210-clock.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/samsung,s5pv210-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Chanwoo Choi <cw00.choi@samsung.com>
11 - Krzysztof Kozlowski <krzk@kernel.org>
12 - Sylwester Nawrocki <s.nawrocki@samsung.com>
13 - Tomasz Figa <tomasz.figa@gmail.com>
16 Expected external clocks, defined in DTS as fixed-rate clocks with a matching
18 - "xxti" - external crystal oscillator connected to XXTI and XXTO pins of
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| D | samsung,s5pv210-audss-clock.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/samsung,s5pv210-audss-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Chanwoo Choi <cw00.choi@samsung.com>
11 - Krzysztof Kozlowski <krzk@kernel.org>
12 - Sylwester Nawrocki <s.nawrocki@samsung.com>
13 - Tomasz Figa <tomasz.figa@gmail.com>
17 include/dt-bindings/clock/s5pv210-audss.h header.
21 const: samsung,s5pv210-audss-clock
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| D | samsung,exynos5410-clock.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/samsung,exynos5410-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Chanwoo Choi <cw00.choi@samsung.com>
11 - Krzysztof Kozlowski <krzk@kernel.org>
12 - Sylwester Nawrocki <s.nawrocki@samsung.com>
13 - Tomasz Figa <tomasz.figa@gmail.com>
16 Expected external clocks, defined in DTS as fixed-rate clocks with a matching
18 - "fin_pll" - PLL input clock from XXTI
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| D | renesas,9series.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas 9-series I2C PCIe clock generators
10 The Renesas 9-series are I2C PCIe clock generators providing
16 - 9FGV0241:
17 0 -- DIF0
18 1 -- DIF1
19 - 9FGV0441:
20 0 -- DIF0
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| /Documentation/devicetree/bindings/clock/ti/ |
| D | fixed-factor-clock.txt | 1 Binding for TI fixed factor rate clock sources.
6 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
10 - compatible : shall be "ti,fixed-factor-clock".
11 - #clock-cells : from common clock binding; shall be set to 0.
12 - ti,clock-div: fixed divider.
13 - ti,clock-mult: fixed multiplier.
14 - clocks: parent clock.
17 - clock-output-names : from common clock binding.
18 - ti,autoidle-shift: bit shift of the autoidle enable bit for the clock,
20 - reg: offset for the autoidle register of this clock, see [2]
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| /Documentation/devicetree/bindings/sound/ |
| D | nvidia,tegra20-i2s.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/sound/nvidia,tegra20-i2s.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
15 - Thierry Reding <treding@nvidia.com>
16 - Jon Hunter <jonathanh@nvidia.com>
20 const: nvidia,tegra20-i2s
28 reset-names:
40 dma-names:
42 - const: rx
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| D | nvidia,tegra20-spdif.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/sound/nvidia,tegra20-spdif.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
16 - Thierry Reding <treding@nvidia.com>
17 - Jon Hunter <jonathanh@nvidia.com>
20 - $ref: dai-common.yaml#
24 const: nvidia,tegra20-spdif
38 clock-names:
40 - const: out
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| D | simple-card.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/sound/simple-card.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
14 frame-master:
15 description: Indicates dai-link frame master.
18 bitclock-master:
19 description: Indicates dai-link bit clock master
22 frame-inversion:
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| /Documentation/netlink/specs/ |
| D | tc.yaml | 1 # SPDX-License-Identifier: ((GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause)
4 protocol: netlink-raw
12 -
16 -
19 -
23 -
26 -
29 -
32 -
35 -
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| /Documentation/devicetree/bindings/serial/ |
| D | arm_sbsa_uart.txt | 7 - compatible: must be "arm,sbsa-uart"
8 - reg: exactly one register range
9 - interrupts: exactly one interrupt specifier
10 - current-speed: the (fixed) baud rate set by the firmware
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| D | xlnx,opb-uartlite.yaml | 1 # SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/serial/xlnx,opb-uartlite.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Peter Korsgaard <jacmet@sunsite.dk>
16 - xlnx,xps-uartlite-1.00.a
17 - xlnx,opb-uartlite-1.00.b
25 port-number:
32 clock-names:
35 current-speed:
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| /Documentation/sound/soc/ |
| D | clocking.rst | 10 ------------
19 power). Other master clocks are fixed at a set frequency (i.e. crystals).
23 ----------
30 runs at exactly the sample rate (LRC = Rate).
32 Bit Clock can be generated as follows:-
34 - BCLK = MCLK / x, or
35 - BCLK = LRC * x, or
36 - BCLK = LRC * Channels * Word Size
40 rate, number of channels and word size) to save on power.
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| /Documentation/devicetree/bindings/net/ |
| D | qcom,ipq4019-mdio.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/net/qcom,ipq4019-mdio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Robert Marko <robert.marko@sartura.hr>
15 - enum:
16 - qcom,ipq4019-mdio
17 - qcom,ipq5018-mdio
19 - items:
20 - enum:
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| /Documentation/devicetree/bindings/ufs/ |
| D | ufs-common.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/ufs/ufs-common.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Alim Akhtar <alim.akhtar@samsung.com>
11 - Avri Altman <avri.altman@wdc.com>
16 clock-names: true
18 freq-table-hz:
21 - description: Minimum frequency for given clock in Hz
22 - description: Maximum frequency for given clock in Hz
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| /Documentation/gpu/amdgpu/display/ |
| D | dc-glossary.rst | 7 'Documentation/gpu/amdgpu/amdgpu-glossary.rst'; if you cannot find it anywhere,
19 Application-Specific Integrated Circuit
49 Cathode Ray Tube Controller - commonly called "Controller" - Generates
108 Display Micro-Controller Unit
111 Display Micro-Controller Unit, version B
120 Dynamic Refresh Rate
135 Fixed Rate Link
225 Transition-Minimized Differential Signaling
234 Variable Refresh Rate
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| /Documentation/devicetree/bindings/net/can/ |
| D | cc770.txt | 4 compatible with the old AN82527 from Intel, but with "bugs" being fixed.
8 - compatible : should be "bosch,cc770" for the CC770 and "intc,82527"
11 - reg : should specify the chip select, address offset and size required
14 - interrupts : property with a value describing the interrupt source
19 - bosch,external-clock-frequency : frequency of the external oscillator
24 - bosch,clock-out-frequency : slock frequency in Hz on the CLKOUT pin.
28 - bosch,slew-rate : slew rate of the CLKOUT signal. If not specified,
31 - bosch,disconnect-rx0-input : see data sheet.
33 - bosch,disconnect-rx1-input : see data sheet.
35 - bosch,disconnect-tx1-output : see data sheet.
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| /Documentation/userspace-api/netlink/ |
| D | netlink-raw.rst | 1 .. SPDX-License-Identifier: BSD-3-Clause
8 families such as ``NETLINK_ROUTE`` which use the ``netlink-raw`` protocol
14 The netlink-raw schema extends the :doc:`genetlink-legacy <genetlink-legacy>`
17 information. The raw netlink families also make use of type-specific
18 sub-messages.
21 -------
29 .. code-block:: yaml
31 # SPDX-License-Identifier: ((GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause)
33 name: rt-addr
34 protocol: netlink-raw
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| /Documentation/devicetree/bindings/spi/ |
| D | jcore,spi.txt | 1 J-Core SPI master
5 - compatible: Must be "jcore,spi2".
7 - reg: Memory region for registers.
9 - #address-cells: Must be 1.
11 - #size-cells: Must be 0.
15 - clocks: If a phandle named "ref_clk" is present, SPI clock speed
17 Necessary only if the input clock rate is something other than a
18 fixed 50 MHz.
20 - clock-names: Clock names, one for each phandle in clocks.
22 See spi-bus.txt for additional properties not specific to this device.
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| /Documentation/peci/ |
| D | peci.rst | 1 .. SPDX-License-Identifier: GPL-2.0-only
13 controller is acting as a PECI originator and the processor - as
15 PECI can be used in both single processor and multiple-processor based
25 ---------
27 PECI Wire interface uses a single wire for self-clocking and data
28 transfer. It does not require any additional control lines - the
29 physical layer is a self-clocked one-wire bus signal that begins each
33 rate established with every message.
35 For PECI Wire, each processor package will utilize unique, fixed
37 have a fixed relationship with the processor socket ID - if one of the
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| /Documentation/networking/ |
| D | radiotap-headers.rst | 1 .. SPDX-License-Identifier: GPL-2.0
8 ------------------------------------
10 Radiotap headers are variable-length and extensible, you can get most of the
19 -----------------------
21 There is a fixed portion at the start which contains a u32 bitmap that defines
29 < 8-byte ieee80211_radiotap_header >
44 --------------------------
46 After the fixed part of the header, the arguments follow for each argument
50 - the arguments are all stored little-endian!
52 - the argument payload for a given argument index has a fixed size. So
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| /Documentation/devicetree/bindings/media/i2c/ |
| D | maxim,max96717.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: MAX96717 CSI-2 to GMSL2 Serializer
11 - Julien Massot <julien.massot@collabora.com>
14 The MAX96717 serializer converts MIPI CSI-2 D-PHY formatted input
16 simultaneously transmit bidirectional control-channel data while forward
18 remotely located deserializer using industry-standard coax or STP
25 The GMSL2 serial link operates at a fixed rate of 3Gbps or 6Gbps in the
27 MAX96717F only supports a fixed rate of 3Gbps in the forward direction.
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