Searched +full:floating +full:- +full:point (Results 1 – 25 of 43) sorted by relevance
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| /Documentation/core-api/ |
| D | floating-point.rst | 1 .. SPDX-License-Identifier: GPL-2.0+
3 Floating-point API
6 Kernel code is normally prohibited from using floating-point (FP) registers or
9 userspace floating-point register state.
15 floating-point usage.
20 floating-point registers may be wider than general-purpose registers.
22 Usability of floating-point code within the kernel is architecture-specific.
24 both with and without a floating-point unit, FPU availability must be checked
27 Several architectures implement the generic kernel floating-point API from
31 Build-time API
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| D | index.rst | 12 massive grab-bag of kerneldoc info left over from the docbook days; it
19 kernel-api
22 printk-basics
23 printk-formats
24 printk-index
25 symbol-namespaces
26 asm-annotations
28 Data structures and low-level utilities
44 circular-buffers
46 generic-radix-tree
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| D | printk-basics.rst | 1 .. SPDX-License-Identifier: GPL-2.0
12 - printk() messages can specify a log level.
14 - the format string, while largely compatible with C99, doesn't follow the
16 (no ``%n`` or floating point conversion specifiers). See :ref:`How to get
17 printk format specifiers right <printk-specifiers>`.
30 +----------------+--------+-----------------------------------------------+
34 +----------------+--------+-----------------------------------------------+
36 +----------------+--------+-----------------------------------------------+
38 +----------------+--------+-----------------------------------------------+
40 +----------------+--------+-----------------------------------------------+
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| /Documentation/arch/arm/nwfpe/ |
| D | netwinder-fpe.rst | 5 The following describes the current state of the NetWinder's floating point
8 In the following nomenclature is used to describe the floating point
14 {P|M|Z} = {round to +infinity,round to -infinity,round to zero},
19 Floating Point Coprocessor Data Transfer Instructions (CPDT)
20 ------------------------------------------------------------
22 LDF/STF - load and store floating
30 LFM/SFM - load and store multiple floating
41 for each floating point register into the memory location given in the
46 Floating Point Coprocessor Register Transfer Instructions (CPRT)
47 ----------------------------------------------------------------
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| D | nwfpe.rst | 5 Floating Point Emulator.
10 working version of all the floating point instructions the compiler
25 The floating point operations are based on SoftFloat Release 2, by
26 John Hauser. SoftFloat is a software implementation of floating-point
27 that conforms to the IEC/IEEE Standard for Binary Floating-point
50 -------------
52 The NetWinder Floating Point Emulator is free software. Everything Rebel.com
57 -------------------------------------------------------------------------------
64 provided by the National Science Foundation under grant MIP-9311980. The
66 a fixed-point vector processor in collaboration with the University of
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| D | todo.rst | 6 POW{cond}<S|D|E>{P,M,Z} Fd, Fn, <Fm,#value> - power
7 RPW{cond}<S|D|E>{P,M,Z} Fd, Fn, <Fm,#value> - reverse power
8 POL{cond}<S|D|E>{P,M,Z} Fd, Fn, <Fm,#value> - polar angle (arctan2)
10 LOG{cond}<S|D|E>{P,M,Z} Fd, <Fm,#value> - logarithm to base 10
11 LGN{cond}<S|D|E>{P,M,Z} Fd, <Fm,#value> - logarithm to base e
12 EXP{cond}<S|D|E>{P,M,Z} Fd, <Fm,#value> - exponent
13 SIN{cond}<S|D|E>{P,M,Z} Fd, <Fm,#value> - sine
14 COS{cond}<S|D|E>{P,M,Z} Fd, <Fm,#value> - cosine
15 TAN{cond}<S|D|E>{P,M,Z} Fd, <Fm,#value> - tangent
16 ASN{cond}<S|D|E>{P,M,Z} Fd, <Fm,#value> - arcsine
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| D | index.rst | 1 .. SPDX-License-Identifier: GPL-2.0
4 NetWinder's floating point emulator
11 netwinder-fpe
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| D | notes.rst | 9 will point it out. The ARM calling conventions require floating point
10 registers f4-f7 to be preserved over a function call. The compiler quite
|
| /Documentation/arch/powerpc/ |
| D | elf_hwcaps.rst | 11 ---------------
46 -------------
56 -------------
65 -------------------
67 HWCAPs are allocated as described in Power Architecture 64-Bit ELF V2 ABI
71 ---------------------------------
74 32-bit CPU
77 64-bit CPU (userspace may be running in 32-bit mode).
87 Floating point facility is available.
105 Embedded Floating Point single precision operations are available.
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| D | kasan.txt | 1 KASAN is supported on powerpc on 32-bit and Radix 64-bit only.
6 KASAN is supported on both hash and nohash MMUs on 32-bit.
18 and Book3E processors floating around on the mailing list, but nothing has been
23 - It would be good to support inline instrumentation so as to be able to catch
26 - Inline instrumentation requires a fixed offset.
28 - Book3S runs code with translations off ("real mode") during boot, including a
29 lot of generic device-tree parsing code which is used to determine MMU
32 - Some code - most notably a lot of KVM code - also runs with translations off
35 - Therefore any offset has to point to memory that is valid with
38 One approach is just to give up on inline instrumentation. This way boot-time
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| D | syscall64-abi.rst | 2 Power Architecture 64-bit Linux system call ABI
9 ----------
17 syscall calling sequence\ [1]_ matches the Power Architecture 64-bit ELF ABI
21 .. [1] Some syscalls (typically low-level management functions) may have
25 ----------
28 There is a maximum of 6 integer parameters to a syscall, passed in r3-r8.
31 ------------
32 - For the sc instruction, both a value and an error condition are returned.
38 - For the scv 0 instruction, the return value indicates failure if it is
39 -4095..-1 (i.e., it is >= -MAX_ERRNO (-4095) as an unsigned comparison),
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| /Documentation/gpu/amdgpu/display/ |
| D | dcn-overview.rst | 10 .. kernel-figure:: dc_pipeline_overview.svg
19 * **Display Pipe and Plane (DPP)**: This block provides pre-blend pixel
24 multiple planes, using global or per-pixel alpha.
38 * **Multi-Media HUB (MMHUBBUB)**: Memory controller interface for DMCUB and DWB
43 the Display Micro-Controller Unit - version B (DMCUB), which is handled via
84 ----------------------
100 a one-to-one mapping of the link encoder to PHY, but we can configure the DCN
106 ---------
114 representation and convert them to a DCN specific floating-point format (i.e.,
115 different from the IEEE floating-point format). In the process, CNVC also
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| /Documentation/arch/arm/ |
| D | mem_alignment.rst | 23 floating point emulation that works about the same way). Fix your code
27 real bad - it changes the behaviour of all unaligned instructions in user
43 slow (think about the floating point emulator) and
50 Note that not all combinations are supported - only values 0 through 5.
|
| /Documentation/devicetree/bindings/riscv/ |
| D | extensions.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: RISC-V ISA extensions
10 - Paul Walmsley <paul.walmsley@sifive.com>
11 - Palmer Dabbelt <palmer@sifive.com>
12 - Conor Dooley <conor@kernel.org>
15 RISC-V has a large number of extensions, some of which are "standard"
16 extensions, meaning they are ratified by RISC-V International, and others
36 Identifies the specific RISC-V instruction set architecture
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| /Documentation/ABI/testing/ |
| D | sysfs-bus-event_source-devices-events | 2 /sys/devices/cpu/events/branch-misses
3 /sys/devices/cpu/events/cache-references
4 /sys/devices/cpu/events/cache-misses
5 /sys/devices/cpu/events/stalled-cycles-frontend
6 /sys/devices/cpu/events/branch-instructions
7 /sys/devices/cpu/events/stalled-cycles-backend
9 /sys/devices/cpu/events/cpu-cycles
13 Contact: Linux kernel mailing list <linux-kernel@vger.kernel.org>
32 Contact: Linux kernel mailing list <linux-kernel@vger.kernel.org>
33 Description: Per-pmu performance monitoring events specific to the running system
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| /Documentation/virt/kvm/s390/ |
| D | s390-pv-dump.rst | 1 .. SPDX-License-Identifier: GPL-2.0
8 -------
27 ------------
41 The vcpu state contains all the important registers, general, floating
42 point, vector, control and tod/timers of a vcpu. The vcpu dump can
52 time of the export does not matter as no re-encryption is
|
| /Documentation/virt/kvm/loongarch/ |
| D | hypercalls.rst | 1 .. SPDX-License-Identifier: GPL-2.0
8 number is put in a0. Up to five arguments may be placed in registers a1 - a5.
20 CPUCFG_KVM_BASE range between 0x40000000 - 0x400000FF is marked as reserved.
24 On a KVM-virtualized Linux system, a read operation on cpucfg() at index
27 Once you have determined that your host is running on a paravirtualization-
34 five generic registers (a1 - a5) used as input parameters. The FP (Floating-
35 point) and vector registers are not utilized as input registers and must
46 a1 1st parameter -
47 a2 2nd parameter -
48 a3 3rd parameter -
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| /Documentation/arch/x86/ |
| D | xstate.rst | 4 The x86 architecture supports floating-point extensions which are
8 Up to AVX-512 and PKRU states, these features are automatically enabled by
15 --------------------------------
17 Legacy userspace libraries often have hard-coded, static sizes for
24 because different CPUs have differently-sized XSAVE buffers. A compiled-in
28 properly-sized altstacks.
31 --------------------------------------------------------------------
37 -ARCH_GET_XCOMP_SUPP
44 -ARCH_GET_XCOMP_PERM
52 -ARCH_REQ_XCOMP_PERM
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| /Documentation/admin-guide/hw-vuln/ |
| D | reg-file-data-sampling.rst | 6 only affects Intel Atom parts(also branded as E-cores). RFDS may allow
7 a malicious actor to infer data values previously used in floating point
9 ability to choose which data is inferred. CVE-2023-28746 is assigned to RFDS.
51 -----------------
54 at C-state transitions.
57 ----------------------------------
62 - Bit 27 - RFDS_NO - When set, processor is not affected by RFDS.
63 - Bit 28 - RFDS_CLEAR - When set, processor is affected by RFDS, and has the
67 ---------------------------------------------
80 -----------------------------
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| /Documentation/filesystems/spufs/ |
| D | spufs.rst | 1 .. SPDX-License-Identifier: GPL-2.0
10 spufs - the SPU file system
26 logical SPU. Users can change permissions on those files, but not actu-
34 set the user owning the mount point, the default is 0 (root).
37 set the group owning the mount point, the default is 0 (root).
43 The files in spufs mostly follow the standard behavior for regular sys-
55 All files support the chmod(2)/fchmod(2) and chown(2)/fchown(2) opera-
81 The first SPU to CPU communication mailbox. This file is read-only and
82 can be read in units of 32 bits. The file can only be used in non-
87 If a count smaller than four is requested, read returns -1 and
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| /Documentation/locking/ |
| D | preempt-locking.rst | 2 Proper Locking Under a Preemptible Kernel: Keeping Kernel Code Preempt-Safe
21 RULE #1: Per-CPU data structures need explicit protection
32 First, since the data is per-CPU, it may not have explicit SMP locking, but
44 Under preemption, the state of the CPU must be protected. This is arch-
48 if the kernel is executing a floating-point instruction and is then preempted.
84 n-times in a code path, and preemption will not be reenabled until the n-th
93 disabling preemption - any cond_resched() or cond_resched_lock() might trigger
95 reschedule. So use this implicit preemption-disabling property only if you
102 cpucache_t *cc; /* this is per-CPU */
105 if (cc && cc->avail) {
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| /Documentation/arch/arm64/ |
| D | sve.rst | 23 -----------
26 tracked per-thread.
34 instructions and registers, and the Linux-specific system interfaces
61 cpu-feature-registers.txt for details.
79 an endianness-invariant layout, with bits [(8 * i + 7) : (8 * i)] encoded at
84 Beware that on big-endian systems this results in a different byte order than
85 for the FPSIMD V-registers, which are stored as single host-endian 128-bit
86 values, with bits [(127 - 8 * i) : (120 - 8 * i)] of the register encoded at
91 -----------------------------
98 * Vector length (VL) = size of a Z-register in bytes
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| /Documentation/devicetree/bindings/powerpc/ |
| D | ibm,powerpc-cpu-features.txt | 3 (skiboot/doc/device-tree/ibm,powerpc-cpu-features/binding.txt)
9 ibm,powerpc-cpu-features binding
19 /cpus/ibm,powerpc-cpu-features node binding
20 -------------------------------------------
22 Node: ibm,powerpc-cpu-features
26 The node name must be "ibm,powerpc-cpu-features".
35 - compatible
38 Definition: "ibm,powerpc-cpu-features"
45 - isa
52 implementation that lacks the "transactional-memory" cpufeature node
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| /Documentation/arch/loongarch/ |
| D | introduction.rst | 1 .. SPDX-License-Identifier: GPL-2.0
7 LoongArch is a new RISC ISA, which is a bit like MIPS or RISC-V. There are
8 currently 3 variants: a reduced 32-bit version (LA32R), a standard 32-bit
9 version (LA32S) and a 64-bit version (LA64). There are 4 privilege levels
17 LoongArch registers include general purpose registers (GPRs), floating point
22 ----
24 LoongArch has 32 GPRs ( ``$r0`` ~ ``$r31`` ); each one is 32-bit wide in LA32
25 and 64-bit wide in LA64. ``$r0`` is hard-wired to zero, and the other registers
26 are not architecturally special. (Except ``$r1``, which is hard-wired as the
30 the LoongArch ELF psABI spec, in :ref:`References <loongarch-references>`:
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| /Documentation/staging/ |
| D | crc32.rst | 5 A CRC is a long-division remainder. You add the CRC to the message,
11 protocols put the end-of-frame flag after the CRC.
15 - We're working in binary, so the digits are only 0 and 1, and
16 - When dividing polynomials, there are no carries. Rather than add and
21 To produce a 32-bit CRC, the divisor is actually a 33-bit CRC polynomial.
24 familiar with the IEEE 754 floating-point format, it's the same idea.)
28 the best error-detecting properties, this should correspond to the
29 order they're actually sent. For example, standard RS-232 serial is
30 little-endian; the most significant bit (sometimes used for parity)
38 back into range. In binary, this is easy - it has to be either 0 or 1,
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