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/Documentation/hwmon/
Daquacomputer_d5next.rst1 .. SPDX-License-Identifier: GPL-2.0-or-later
3 Kernel driver aquacomputer-d5next
10 * Aquacomputer Farbwerk RGB controller
11 * Aquacomputer Farbwerk 360 RGB controller
12 * Aquacomputer Octo fan controller
13 * Aquacomputer Quadro fan controller
14 * Aquacomputer High Flow Next sensor
18 * Aquacomputer Poweradjust 3 fan controller
19 * Aquacomputer High Flow USB flow meter
20 * Aquacomputer MPS Flow devices
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/Documentation/devicetree/bindings/serial/
Dmilbeaut-uart.txt1 Socionext Milbeaut UART controller
4 - compatible: should be "socionext,milbeaut-usio-uart".
5 - reg: offset and length of the register set for the device.
6 - interrupts: two interrupts specifier.
7 - interrupt-names: should be "rx", "tx".
8 - clocks: phandle to the input clock.
11 - auto-flow-control: flow control enable.
15 compatible = "socionext,milbeaut-usio-uart";
18 interrupt-names = "rx", "tx";
20 auto-flow-control;
Dsocionext,uniphier-uart.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/serial/socionext,uniphier-uart.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: UniPhier UART controller
10 - Masahiro Yamada <yamada.masahiro@socionext.com>
14 const: socionext,uniphier-uart
28 auto-flow-control:
29 description: enable automatic flow control support.
33 - compatible
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Dst,asc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Patrice Chotard <patrice.chotard@foss.st.com>
13 - $ref: serial.yaml#
28 st,hw-flow-ctrl:
29 description: When set, enable hardware flow control.
32 st,force-m1:
33 description: When set, force asc to be in Mode-1. This is recommended for
38 - compatible
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/Documentation/core-api/
Dgenericirq.rst7 :Copyright: |copy| 2005-2010: Thomas Gleixner
8 :Copyright: |copy| 2005-2006: Ingo Molnar
15 handle all the different types of interrupt controller hardware. Device
29 __do_IRQ() super-handler, which is able to deal with every type of
36 - Level type
38 - Edge type
40 - Simple type
44 - Fast EOI type
46 In the SMP world of the __do_IRQ() super-handler another type was
49 - Per CPU type
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/Documentation/networking/device_drivers/ethernet/intel/
Di40e.rst1 .. SPDX-License-Identifier: GPL-2.0+
4 Linux Base Driver for the Intel(R) Ethernet Controller 700 Series
8 Copyright(c) 1999-2018 Intel Corporation.
13 - Overview
14 - Identifying Your Adapter
15 - Intel(R) Ethernet Flow Director
16 - Additional Configurations
17 - Known Issues
18 - Support
34 * Intel(R) Ethernet Controller X710
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Dfm10k.rst1 .. SPDX-License-Identifier: GPL-2.0+
4 Linux Base Driver for Intel(R) Ethernet Multi-host Controller
8 Copyright(c) 2015-2018 Intel Corporation.
12 - Identifying Your Adapter
13 - Additional Configurations
14 - Performance Tuning
15 - Known Issues
16 - Support
21 Ethernet Multi-host Controller.
28 Flow Control
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Dixgbe.rst1 .. SPDX-License-Identifier: GPL-2.0+
8 Copyright(c) 1999-2018 Intel Corporation.
13 - Identifying Your Adapter
14 - Command Line Parameters
15 - Additional Configurations
16 - Known Issues
17 - Support
23 * Intel(R) Ethernet Controller 82598
24 * Intel(R) Ethernet Controller 82599
25 * Intel(R) Ethernet Controller X520
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Dice.rst1 .. SPDX-License-Identifier: GPL-2.0+
4 Linux Base Driver for the Intel(R) Ethernet Controller 800 Series
8 Copyright(c) 2018-2021 Intel Corporation.
13 - Overview
14 - Identifying Your Adapter
15 - Important Notes
16 - Additional Features & Configurations
17 - Performance Optimization
28 This driver supports XDP (Express Data Path) and AF_XDP zero-copy. Note that
43 -------------------------------------------
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/Documentation/devicetree/bindings/interrupt-controller/
Dcirrus,clps711x-intc.txt1 Cirrus Logic CLPS711X Interrupt Controller
5 - compatible: Should be "cirrus,ep7209-intc".
6 - reg: Specifies base physical address of the registers set.
7 - interrupt-controller: Identifies the node as an interrupt controller.
8 - #interrupt-cells: Specifies the number of cells needed to encode an
13 ---------------------------
20 8: TC1OI TC1 under flow
21 9: TC2OI TC2 under flow
36 intc: interrupt-controller {
37 compatible = "cirrus,ep7312-intc", "cirrus,ep7209-intc";
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/Documentation/devicetree/bindings/soc/tegra/
Dnvidia,tegra20-flowctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/tegra/nvidia,tegra20-flowctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra Flow Controller
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
16 - enum:
17 - nvidia,tegra20-flowctrl
18 - nvidia,tegra30-flowctrl
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/Documentation/devicetree/bindings/hsi/
Dclient-devices.txt7 - hsi-channel-ids: A list of channel ids
9 - hsi-rx-mode: Receiver Bit transmission mode ("stream" or "frame")
10 - hsi-tx-mode: Transmitter Bit transmission mode ("stream" or "frame")
11 - hsi-mode: May be used instead hsi-rx-mode and hsi-tx-mode if
14 - hsi-speed-kbps: Max bit transmission speed in kbit/s
15 - hsi-flow: RX flow type ("synchronized" or "pipeline")
16 - hsi-arb-mode: Arbitration mode for TX frame ("round-robin", "priority")
20 - hsi-channel-names: A list with one name per channel specified in the
21 hsi-channel-ids property
26 hsi-controller {
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/Documentation/devicetree/bindings/net/nfc/
Dmarvell,nci.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Marvell International Ltd. NCI NFC controller
10 - Krzysztof Kozlowski <krzk@kernel.org>
15 - marvell,nfc-i2c
16 - marvell,nfc-spi
17 - marvell,nfc-uart
19 hci-muxed:
30 reset-n-io:
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/Documentation/devicetree/bindings/crypto/
Damlogic,gxl-crypto.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/crypto/amlogic,gxl-crypto.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Corentin Labbe <clabbe@baylibre.com>
15 - const: amlogic,gxl-crypto
22 - description: Interrupt for flow 0
23 - description: Interrupt for flow 1
28 clock-names:
32 - compatible
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/Documentation/gpu/
Dkomeda-kms.rst1 .. SPDX-License-Identifier: GPL-2.0
23 -----
30 ------
39 -------------------
47 --------------------------
52 -----------------------------
56 Timing controller (timing_ctrlr)
57 --------------------------------
58 Final stage of display pipeline, Timing controller is not for the pixel
62 ------
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/Documentation/networking/device_drivers/ethernet/freescale/
Ddpaa.rst1 .. SPDX-License-Identifier: GPL-2.0
8 - Madalin Bucur <madalin.bucur@nxp.com>
9 - Camelia Groza <camelia.groza@nxp.com>
13 - DPAA Ethernet Overview
14 - DPAA Ethernet Supported SoCs
15 - Configuring DPAA Ethernet in your kernel
16 - DPAA Ethernet Frame Processing
17 - DPAA Ethernet Features
18 - DPAA IRQ Affinity and Receive Side Scaling
19 - Debugging
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/Documentation/networking/
Diso15765-2.rst1 .. SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
4 ISO 15765-2 (ISO-TP)
10 ISO 15765-2, also known as ISO-TP, is a transport protocol specifically defined
12 industry, for example as the transport protocol for UDSonCAN (ISO 14229-3) or
13 emission-related diagnostic services (ISO 15031-5).
15 ISO-TP can be used both on CAN CC (aka Classical CAN) and CAN FD (CAN with
21 -------------------
23 * ISO 15765-2:2024 : Road vehicles - Diagnostic communication over Controller
27 ----------
29 In its simplest form, ISO-TP is based on two kinds of addressing modes for the
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/Documentation/devicetree/bindings/pinctrl/
Dpinctrl-sirf.txt1 CSR SiRFprimaII pinmux controller
4 - compatible : "sirf,prima2-pinctrl"
5 - reg : Address range of the pinctrl registers
6 - interrupts : Interrupts used by every GPIO group
7 - gpio-controller : Indicates this device is a GPIO controller
8 - interrupt-controller : Marks the device node as an interrupt controller
10 - sirf,pullups : if n-th bit of m-th bank is set, set a pullup on GPIO-n of bank m
11 - sirf,pulldowns : if n-th bit of m-th bank is set, set a pulldown on GPIO-n of bank m
13 Please refer to pinctrl-bindings.txt in this directory for details of the common
19 Required subnode-properties:
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/Documentation/devicetree/bindings/sound/
Dmvebu-audio.txt1 * mvebu (Kirkwood, Dove, Armada 370) audio controller
5 - compatible:
6 "marvell,kirkwood-audio" for Kirkwood platforms
7 "marvell,dove-audio" for Dove platforms
8 "marvell,armada370-audio" for Armada 370 platforms
9 "marvell,armada-380-audio" for Armada 38x platforms
11 - reg: physical base address of the controller and length of memory mapped
13 With "marvell,armada-380-audio" two other regions are required:
15 (named "pll_regs") and the second one ("soc_ctrl") - for register
18 - interrupts:
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Dst,stm32-spdifrx.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/sound/st,stm32-spdifrx.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Olivier Moysan <olivier.moysan@foss.st.com>
13 The SPDIFRX peripheral, is designed to receive an S/PDIF flow compliant with
14 IEC-60958 and IEC-61937.
17 - $ref: dai-common.yaml#
22 - st,stm32h7-spdifrx
24 "#sound-dai-cells":
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/Documentation/devicetree/bindings/dma/ti/
Dk3-pktdma.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
5 ---
6 $id: http://devicetree.org/schemas/dma/ti/k3-pktdma.yaml#
7 $schema: http://devicetree.org/meta-schemas/core.yaml#
12 - Peter Ujfalusi <peter.ujfalusi@gmail.com>
16 mode channels of K3 UDMA-P.
17 PKTDMA only includes Split channels to service PSI-L based peripherals.
19 The peripherals can be PSI-L native or legacy, non PSI-L native peripherals
20 with PDMAs. PDMA is tasked to act as a bridge between the PSI-L fabric and the
27 - $ref: /schemas/dma/dma-controller.yaml#
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/Documentation/devicetree/bindings/arm/mediatek/
Dmediatek,mt7622-wed.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/arm/mediatek/mediatek,mt7622-wed.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: MediaTek Wireless Ethernet Dispatch Controller for MT7622
10 - Lorenzo Bianconi <lorenzo@kernel.org>
11 - Felix Fietkau <nbd@nbd.name>
14 The mediatek wireless ethernet dispatch controller can be configured to
16 and implement hardware flow offloading from ethernet to WLAN.
21 - enum:
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/Documentation/devicetree/bindings/dma/xilinx/
Dxlnx,zynqmp-dma-1.0.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/dma/xilinx/xlnx,zynqmp-dma-1.0.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 memory to device and device to memory transfers. It also has flow
15 - Michael Tretter <m.tretter@pengutronix.de>
16 - Harini Katakam <harini.katakam@amd.com>
17 - Radhey Shyam Pandey <radhey.shyam.pandey@amd.com>
20 - $ref: ../dma-controller.yaml#
23 "#dma-cells":
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/Documentation/devicetree/bindings/net/
Dloongson,ls1b-gmac.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/loongson,ls1b-gmac.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Loongson-1B Gigabit Ethernet MAC Controller
10 - Keguang Zhang <keguang.zhang@gmail.com>
13 Loongson-1B Gigabit Ethernet MAC Controller is based on
17 - Dual 10/100/1000Mbps GMAC controllers
18 - Full-duplex operation (IEEE 802.3x flow control automatic transmission)
19 - Half-duplex operation (CSMA/CD Protocol and back-pressure support)
[all …]
Dloongson,ls1c-emac.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/loongson,ls1c-emac.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Loongson-1C Ethernet MAC Controller
10 - Keguang Zhang <keguang.zhang@gmail.com>
13 Loongson-1C Ethernet MAC Controller is based on
17 - 10/100Mbps
18 - Full-duplex operation (IEEE 802.3x flow control automatic transmission)
19 - Half-duplex operation (CSMA/CD Protocol and back-pressure support)
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