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/Documentation/driver-api/fpga/
Dfpga-region.rst1 FPGA Region
5 --------
7 This document is meant to be a brief overview of the FPGA region API usage. A
11 For the purposes of this API document, let's just say that a region associates
12 an FPGA Manager and a bridge (or bridges) with a reprogrammable region of an
13 FPGA or the whole FPGA. The API provides a way to register a region and to
14 program a region.
16 Currently the only layer above fpga-region.c in the kernel is the Device Tree
17 support (of-fpga-region.c) described in [#f1]_. The DT support layer uses regions
18 to program the FPGA and then DT to handle enumeration. The common region code
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Dintro.rst4 The FPGA subsystem supports reprogramming FPGAs dynamically under
5 Linux. Some of the core intentions of the FPGA subsystems are:
7 * The FPGA subsystem is vendor agnostic.
9 * The FPGA subsystem separates upper layers (userspace interfaces and
11 FPGA.
16 other users. Write the linux-fpga mailing list and maintainers and
23 FPGA Manager
24 ------------
26 If you are adding a new FPGA or a new method of programming an FPGA,
27 this is the subsystem for you. Low level FPGA manager drivers contain
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Dfpga-programming.rst1 In-kernel API for FPGA Programming
5 --------
7 The in-kernel API for FPGA programming is a combination of APIs from
8 FPGA manager, bridge, and regions. The actual function used to
9 trigger FPGA programming is fpga_region_program_fpga().
12 the FPGA manager and bridges. It will:
14 * lock the region's mutex
15 * lock the mutex of the region's FPGA manager
16 * build a list of FPGA bridges if a method has been specified to do so
18 * program the FPGA using info passed in :c:expr:`fpga_region->info`.
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Dindex.rst2 FPGA Subsystem
11 fpga-mgr
12 fpga-bridge
13 fpga-region
14 fpga-programming
/Documentation/devicetree/bindings/fpga/
Dfpga-region.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/fpga/fpga-region.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: FPGA Region
10 - Michal Simek <michal.simek@amd.com>
14 - Introduction
15 - Terminology
16 - Sequence
17 - FPGA Region
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Dlattice-machxo2-spi.txt1 Lattice MachXO2 Slave SPI FPGA Manager
9 - compatible: should contain "lattice,machxo2-slave-spi"
10 - reg: spi chip select of the FPGA
12 Example for full FPGA configuration:
14 fpga-region0 {
15 compatible = "fpga-region";
16 fpga-mgr = <&fpga_mgr_spi>;
17 #address-cells = <0x1>;
18 #size-cells = <0x1>;
24 fpga_mgr_spi: fpga-mgr@0 {
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Dxlnx,pr-decoupler.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/fpga/xlnx,pr-decoupler.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Nava kishore Manne <nava.kishore.manne@amd.com>
13 - $ref: fpga-bridge.yaml#
17 decouplers/fpga bridges. The controller can decouple/disable the bridges
22 is compatible with the Xilinx LogiCORE pr-decoupler. The Dynamic Function
24 bridge. The controller safely handles AXI4MM and AXI4-Lite interfaces on a
28 Please refer to fpga-region.txt and fpga-bridge.txt in this directory for
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/Documentation/ABI/testing/
Dsysfs-class-fpga-region1 What: /sys/class/fpga_region/<region>/compat_id
5 Description: FPGA region id for compatibility check, e.g. compatibility
6 of the FPGA reconfiguration hardware and image. This value
8 FPGA region. This interface returns the compat_id value or
9 just error code -ENOENT in case compat_id is not used.
Dsysfs-platform-dfl-fme1 What: /sys/bus/platform/devices/dfl-fme.0/ports_num
5 Description: Read-only. One DFL FPGA device may have more than 1
7 number of ports on the FPGA device when read it.
9 What: /sys/bus/platform/devices/dfl-fme.0/bitstream_id
13 Description: Read-only. It returns Bitstream (static FPGA region)
15 and other information of this static FPGA region.
17 What: /sys/bus/platform/devices/dfl-fme.0/bitstream_metadata
21 Description: Read-only. It returns Bitstream (static FPGA region) meta
23 information of this static FPGA region.
25 What: /sys/bus/platform/devices/dfl-fme.0/cache_size
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/Documentation/fpga/
Ddfl.rst2 FPGA Device Feature List (DFL) Framework Overview
7 - Enno Luebbers <enno.luebbers@intel.com>
8 - Xiao Guangrong <guangrong.xiao@linux.intel.com>
9 - Wu Hao <hao.wu@intel.com>
10 - Xu Yilun <yilun.xu@intel.com>
12 The Device Feature List (DFL) FPGA framework (and drivers according to
15 configure, enumerate, open and access FPGA accelerators on platforms which
17 enables system level management functions such as FPGA reconfiguration.
24 walk through these predefined data structures to enumerate FPGA features:
25 FPGA Interface Unit (FIU), Accelerated Function Unit (AFU) and Private Features,
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/Documentation/devicetree/bindings/gpio/
Dgpio-ts4900.txt1 * Technologic Systems I2C-FPGA's GPIO controller bindings
3 This bindings describes the GPIO controller for Technologic's FPGA core.
4 TS-4900's FPGA encodes the GPIO state on 3 bits, whereas the TS-7970's FPGA
8 - compatible: Should be one of the following
9 "technologic,ts4900-gpio"
10 "technologic,ts7970-gpio"
11 - reg: Physical base address of the controller and length
12 of memory mapped region.
13 - #gpio-cells: Should be two. The first cell is the pin number.
14 - gpio-controller: Marks the device node as a gpio controller.
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Dgpio-ts4800.txt1 * TS-4800 FPGA's GPIO controller bindings
4 - compatible: Must be "technologic,ts4800-gpio".
5 - #gpio-cells: Should be two. The first cell is the pin number.
6 - reg: Physical base address of the controller and length
7 of memory mapped region.
10 - ngpios: See "gpio.txt"
15 compatible = "technologic,ts4800-gpio";
18 gpio-controller;
19 #gpio-cells = <2>;
/Documentation/devicetree/bindings/input/touchscreen/
Dts4800-ts.txt1 * TS-4800 Touchscreen bindings
4 - compatible: must be "technologic,ts4800-ts"
5 - reg: physical base address of the controller and length of memory mapped
6 region.
7 - syscon: phandle / integers array that points to the syscon node which
8 describes the FPGA's syscon registers.
9 - phandle to FPGA's syscon
10 - offset to the touchscreen register
11 - offset to the touchscreen enable bit
/Documentation/devicetree/bindings/firmware/
Dintel,stratix10-svc.txt3 Intel Stratix10 SoC is composed of a 64 bit quad-core ARM Cortex A53 hard
4 processor system (HPS) and Secure Device Manager (SDM). When the FPGA is
7 configuration data from that location and perform the FPGA configuration.
17 the services for FPGA configuration, QSPI, Crypto and warm reset. Service layer
22 -------------------
26 - compatible: "intel,stratix10-svc" or "intel,agilex-svc"
27 - method: smc or hvc
28 smc - Secure Monitor Call
29 hvc - Hypervisor Call
30 - memory-region:
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/Documentation/devicetree/bindings/interrupt-controller/
Dtechnologic,ts4800.txt1 TS-4800 FPGA interrupt controller
3 TS-4800 FPGA has an internal interrupt controller. When one of the
8 - compatible: should be "technologic,ts4800-irqc"
9 - interrupt-controller: identifies the node as an interrupt controller
10 - reg: physical base address of the controller and length of memory mapped
11 region
12 - #interrupt-cells: specifies the number of cells needed to encode an interrupt
14 - interrupts: specifies the interrupt line in the interrupt-parent controller
/Documentation/devicetree/bindings/display/
Dxylon,logicvc-display.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/display/xylon,logicvc-display.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Paul Kocialkowski <paul.kocialkowski@bootlin.com>
16 with Xilinx Zynq-7000 SoCs and Xilinx FPGAs.
18 Because the controller is intended for use in a FPGA, most of the
20 synthesis time. As a result, many of the device-tree bindings are meant to
24 Layers are declared in the "layers" sub-node and have dedicated configuration.
32 - xylon,logicvc-3.02.a-display
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/Documentation/mm/
Dhmm.rst5 Provide infrastructure and helpers to integrate non-conventional memory (device
14 heterogeneous computing where GPU, DSP, or FPGA are used to perform various
21 CPU page-table mirroring works and the purpose of HMM in this context. The
37 i.e., one in which any application memory region can be used by a device
52 complex data set needs to re-map all the pointer relations between each of its
95 two-way cache coherency between CPU and device and allow all atomic operations the
115 allocate a buffer (or use a pool of pre-allocated buffers) and write GPU
155 During the ops->invalidate() callback the device driver must perform the
164 It will trigger a page fault on missing or read-only entries if write access is
178 if (!mmget_not_zero(interval_sub->notifier.mm))
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