Searched +full:frame +full:- +full:master (Results 1 – 25 of 47) sorted by relevance
12
| /Documentation/devicetree/bindings/sound/ |
| D | mikroe,mikroe-proto.txt | 1 Mikroe-PROTO audio board
4 - compatible: "mikroe,mikroe-proto"
5 - dai-format: Must be "i2s".
6 - i2s-controller: The phandle of the I2S controller.
7 - audio-codec: The phandle of the WM8731 audio codec.
9 - model: The user-visible name of this sound complex.
10 - bitclock-master: Indicates dai-link bit clock master; for details see simple-card.txt (1).
11 - frame-master: Indicates dai-link frame master; for details see simple-card.txt (1).
13 (1) : There must be the same master for both bit and frame clocks.
17 compatible = "mikroe,mikroe-proto";
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| D | simple-card.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/sound/simple-card.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
14 frame-master:
15 description: Indicates dai-link frame master.
18 bitclock-master:
19 description: Indicates dai-link bit clock master
22 frame-inversion:
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| D | audio-graph-port.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/sound/audio-graph-port.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
15 port-base:
17 - $ref: /schemas/graph.yaml#/$defs/port-base
18 - $ref: /schemas/sound/dai-params.yaml#
20 mclk-fs:
21 $ref: simple-card.yaml#/definitions/mclk-fs
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| D | fsl-asoc-card.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/sound/fsl-asoc-card.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
28 - Shengjiu Wang <shengjiu.wang@nxp.com>
33 - items:
34 - enum:
35 - fsl,imx-sgtl5000
36 - fsl,imx25-pdk-sgtl5000
37 - fsl,imx53-cpuvo-sgtl5000
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| D | fsl,sai.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Shengjiu Wang <shengjiu.wang@nxp.com>
15 serial interfaces with frame synchronization such as I2S, AC97, TDM, and
21 - items:
22 - enum:
23 - fsl,imx6ul-sai
24 - fsl,imx7d-sai
25 - const: fsl,imx6sx-sai
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| D | amlogic,gx-sound-card.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/sound/amlogic,gx-sound-card.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jerome Brunet <jbrunet@baylibre.com>
13 - $ref: sound-card-common.yaml#
18 - const: amlogic,gx-sound-card
20 audio-aux-devs:
21 $ref: /schemas/types.yaml#/definitions/phandle-array
24 audio-widgets:
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| D | amlogic,axg-sound-card.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/sound/amlogic,axg-sound-card.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jerome Brunet <jbrunet@baylibre.com>
13 - $ref: sound-card-common.yaml#
17 const: amlogic,axg-sound-card
19 audio-aux-devs:
20 $ref: /schemas/types.yaml#/definitions/phandle-array
23 audio-widgets:
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| /Documentation/sound/soc/ |
| D | clocking.rst | 9 Master Clock
10 ------------
12 Every audio subsystem is driven by a master clock (sometimes referred to as MCLK
13 or SYSCLK). This audio master clock can be derived from a number of sources
17 Some master clocks (e.g. PLLs and CPU based clocks) are configurable in that
19 power). Other master clocks are fixed at a set frequency (i.e. crystals).
23 ----------
28 The DAI also has a frame clock to signal the start of each audio frame. This
29 clock is sometimes referred to as LRC (left right clock) or FRAME. This clock
32 Bit Clock can be generated as follows:-
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| D | dai.rst | 16 frame (FRAME) (usually 48kHz) is always driven by the controller. Each AC97
17 frame is 21uS long and is divided into 13 time slots.
29 controller or CODEC can drive (master) the BCLK and LRC clock lines. Bit clock
30 usually varies depending on the sample rate and the master system clock
35 I2S has several different operating modes:-
58 Common PCM operating modes:-
61 MSB is transmitted on falling edge of first BCLK after FRAME/SYNC.
64 MSB is transmitted on rising edge of FRAME/SYNC.
|
| /Documentation/driver-api/soundwire/ |
| D | error_handling.rst | 13 1. Bus clash or parity errors: This mechanism relies on low-level detectors
20 impact its audibility (most-significant bits will be more impacted in PCM),
33 current frame. A NAK indicates that the command was in error and will not
34 be applied. In case of a bad programming (command sent to non-existent
35 Slave or to a non-implemented register) or electrical issue, no response
36 signals the command was ignored. Some Master implementations allow for a
40 reset and re-enumerate all devices.
47 driver will return a -ETIMEOUT. Such timeouts are symptoms of a faulty
57 such as frame reconfiguration would be handled at different times). A global
58 hard-reset might be the best solution.
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| D | stream.rst | 24 -------------------------
26 -------------------------
28 Example 1: Stereo Stream with L and R channels is rendered from Master to
29 Slave. Both Master and Slave is using single port. ::
31 +---------------+ Clock Signal +---------------+
32 | Master +----------------------------------+ Slave |
36 | L + R +----------------------------------+ L + R |
38 +---------------+ +-----------------------> +---------------+
42 Master. Both Master and Slave is using single port. ::
45 +---------------+ Clock Signal +---------------+
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| /Documentation/networking/ |
| D | generic-hdlc.rst | 1 .. SPDX-License-Identifier: GPL-2.0
12 1. Frame Relay (ANSI, CCITT, Cisco and no LMI)
14 - Normal (routed) and Ethernet-bridged (Ethernet device emulation)
16 - ARP support (no InARP support in the kernel - there is an
17 experimental InARP user-space daemon available on:
20 2. raw HDLC - either IP (IPv4) interface or Ethernet device emulation
25 Generic HDLC is a protocol driver only - it needs a low-level driver
28 Ethernet device emulation (using HDLC or Frame-Relay PVC) is compatible
40 gcc -O2 -Wall -o sethdlc sethdlc.c
45 and add any required PVCs if using Frame Relay.
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| D | cdc_mbim.rst | 1 .. SPDX-License-Identifier: GPL-2.0
4 cdc_mbim - Driver for CDC MBIM Mobile Broadband modems
24 -----------
26 :Valid Range: N/Y (0-1)
51 - mbimcli (included with the libmbim [3] library), and
52 - ModemManager [4]
57 - open the control channel
58 - configure network connection settings
59 - connect to network
60 - configure IP interface
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| /Documentation/userspace-api/media/v4l/ |
| D | metafmt-d4xx.rst | 1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
3 .. _v4l2-meta-fmt-d4xx:
15 Intel D4xx (D435, D455 and others) cameras include per-frame metadata in their UVC
27 per frame, therefore their headers cannot be larger than 255 bytes.
37 .. flat-table:: D4xx metadata
39 :header-rows: 1
40 :stub-columns: 0
42 * - **Field**
43 - **Description**
44 * - :cspan:`1` *Depth Control*
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| D | dev-encoder.rst | 1 .. SPDX-License-Identifier: GPL-2.0 OR GFDL-1.1-no-invariants-or-later
6 Memory-to-Memory Stateful Video Encoder Interface
12 further post-processing by the client.
34 5. Single-planar API (see :ref:`planar-apis`) and applicable structures may be
35 used interchangeably with multi-planar API, unless specified otherwise,
47 Refer to :ref:`decoder-glossary`.
52 .. kernel-render:: DOT
65 qi -> Initialization [ label = "open()" ];
67 Initialization -> Encoding [ label = "Both queues streaming" ];
69 Encoding -> Drain [ label = "V4L2_ENC_CMD_STOP" ];
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| D | dev-decoder.rst | 1 .. SPDX-License-Identifier: GPL-2.0
6 Memory-to-Memory Stateful Video Decoder Interface
9 A stateful video decoder takes complete chunks of the bytestream (e.g. Annex-B
34 5. Single-planar API (see :ref:`planar-apis`) and applicable structures may be
35 used interchangeably with multi-planar API, unless specified otherwise,
44 .. _decoder-glossary:
79 Good at sub-partitioning the picture into variable sized structures.
83 coded format includes a feature of frame reordering; for decoders,
97 raw frame available for reference in further decoding steps.
103 Instantaneous Decoder Refresh; a type of a keyframe in an H.264/HEVC-encoded
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| /Documentation/admin-guide/media/ |
| D | pci-cardlist.rst | 1 .. SPDX-License-Identifier: GPL-2.0
9 - Vendor ID and device ID;
10 - Subsystem ID and Subsystem device ID;
12 The ``lspci -nn`` command allows identifying the vendor/device PCI IDs:
14 .. code-block:: none
15 :emphasize-lines: 3
17 $ lspci -nn
23 …02:02.0 Multimedia video controller [0400]: Conexant Systems, Inc. CX23418 Single-Chip MPEG-2 Enco…
27 The subsystem IDs can be obtained using ``lspci -vn``
29 .. code-block:: none
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| D | ipu3.rst | 1 .. SPDX-License-Identifier: GPL-2.0
24 ImgU). The CIO2 driver is available as drivers/media/pci/intel/ipu3/ipu3-cio2*
36 Both of the drivers implement V4L2, Media Controller and V4L2 sub-device
38 MIPI CSI-2 interfaces through V4L2 sub-device sensor drivers.
44 interface to the user space. There is a video node for each CSI-2 receiver,
47 The CIO2 contains four independent capture channel, each with its own MIPI CSI-2
48 receiver and DMA engine. Each channel is modelled as a V4L2 sub-device exposed
49 to userspace as a V4L2 sub-device node and has two pads:
53 .. flat-table::
54 :header-rows: 1
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| /Documentation/devicetree/bindings/misc/ |
| D | ifm-csi.txt | 4 - compatible: "ifm,o2d-csi"
5 - reg: specifies sensor chip select number and associated address range
6 - interrupts: external interrupt line number and interrupt sense mode
7 of the interrupt line signaling frame valid events
8 - gpios: three gpio-specifiers for "capture", "reset" and "master enable"
10 - ifm,csi-clk-handle: the phandle to a node in the DT describing the sensor
12 - ifm,csi-addr-bus-width: address bus width (valid values are 16, 24, 25)
13 - ifm,csi-data-bus-width: data bus width (valid values are 8 and 16)
14 - ifm,csi-wait-cycles: sensor bus wait cycles
17 - ifm,csi-byte-swap: if this property is present, the byte swapping on
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| /Documentation/networking/device_drivers/can/ctu/ |
| D | ctucanfd-driver.rst | 1 .. SPDX-License-Identifier: GPL-2.0-or-later
10 ------------------------
19 `Vivado integration <https://gitlab.fel.cvut.cz/canbus/zynq/zynq-can-sja1000-top>`_
20 and Intel Cyclone V 5CSEMA4U23C6 based DE0-Nano-SoC Terasic board
21 `QSys integration <https://gitlab.fel.cvut.cz/canbus/intel-soc-ctucanfd>`_
23 `PCIe integration <https://gitlab.fel.cvut.cz/canbus/pcie-ctucanfd>`_ of the core.
31 accepted into QEMU mainline. See QEMU `CAN emulation support <https://www.qemu.org/docs/master/syst…
33 version of emulation support can be cloned from ctu-canfd branch of QEMU local
34 development `repository <https://gitlab.fel.cvut.cz/canbus/qemu-canbus>`_.
38 ---------------
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| /Documentation/devicetree/bindings/net/bluetooth/ |
| D | brcm,bluetooth.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Linus Walleij <linus.walleij@linaro.org>
13 This binding describes Broadcom UART-attached bluetooth chips.
18 - items:
19 - enum:
20 - infineon,cyw43439-bt
21 - const: brcm,bcm4329-bt
22 - enum:
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| /Documentation/gpu/ |
| D | komeda-kms.rst | 1 .. SPDX-License-Identifier: GPL-2.0
23 -----
30 ------
35 frame and then feed the output data into wb_layer which will then write it
39 -------------------
41 frame. its output frame can be fed into post image processor for showing it on
44 the display frame first and then write to memory.
47 --------------------------
52 -----------------------------
53 Post image processor adjusts frame data like gamma and color space to fit the
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| /Documentation/devicetree/bindings/net/ |
| D | lantiq,pef2256.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Herve Codina <herve.codina@bootlin.com>
20 - const: lantiq,pef2256
27 - description: Master Clock
28 - description: System Clock Receive
29 - description: System Clock Transmit
31 clock-names:
33 - const: mclk
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| /Documentation/devicetree/bindings/display/ |
| D | st,stih4xx.txt | 3 - sti-vtg: video timing generator
5 - compatible: "st,vtg"
6 - reg: Physical base address of the IP registers and length of memory mapped region.
8 - interrupts : VTG interrupt number to the CPU.
9 - st,slave: phandle on a slave vtg
11 - sti-vtac: video timing advanced inter dye communication Rx and TX
13 - compatible: "st,vtac-main" or "st,vtac-aux"
14 - reg: Physical base address of the IP registers and length of memory mapped region.
15 - clocks: from common clock binding: handle hardware IP needed clocks, the
17 See ../clocks/clock-bindings.txt for details.
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| /Documentation/bpf/ |
| D | map_xskmap.rst | 1 .. SPDX-License-Identifier: GPL-2.0-only
9 - ``BPF_MAP_TYPE_XSKMAP`` was introduced in kernel version 4.18
18 .. code-block:: none
20 +---------------------------------------------------+
21 | xsk A | xsk B | xsk C |<---+ User space
24 +---------------------------------------------------+ |
26 +---------------------------------------------------+ |
29 | +---------+ +=============+ | |
31 | | | +-------------+ | |
33 | | BPF |-- redirect -->+-------------+-------------+
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