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/Documentation/devicetree/bindings/timer/
Darm,arch_timer_mmio.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Marc Zyngier <marc.zyngier@arm.com>
11 - Mark Rutland <mark.rutland@arm.com>
15 frames with a physical and optional virtual timer per frame.
22 - enum:
23 - arm,armv7-timer-mem
27 description: The control frame base address
29 '#address-cells':
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/Documentation/userspace-api/media/v4l/
Dpixfmt-compressed.rst1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
8 .. _compressed-formats:
18 .. flat-table:: Compressed Image Formats
19 :header-rows: 1
20 :stub-columns: 0
23 * - Identifier
24 - Code
25 - Details
26 * .. _V4L2-PIX-FMT-JPEG:
28 - ``V4L2_PIX_FMT_JPEG``
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Ddev-stateless-decoder.rst1 .. SPDX-License-Identifier: GPL-2.0
6 Memory-to-memory Stateless Video Decoder Interface
10 between processed frames. This means that each frame is decoded independently
18 This section describes how user-space ("the client") is expected to communicate
24 Stateless decoders make use of the :ref:`media-request-api`. A stateless
30 frame may be the result of several decode requests (for instance, H.264 streams
31 with multiple slices per frame). Decoders that support such formats must also
45 codec-specific capability controls (such as H.264 profiles) to the set
55 formats may depend on the value of some codec-dependent controls.
110 frame buffer resolution for the decoded frames.
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Dfunc-read.rst1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
4 .. _func-read:
13 v4l2-read - Read from a V4L2 device
18 .. code-block:: c
34 Max number of bytes to read
45 :c:func:`read()` call will provide at most one frame (two fields)
65 reading, or the capture rate must fall below the nominal frame rate of
72 previously, not read frame, and returns the frame being received at the
76 :c:func:`read()` call. The frame being received at :c:func:`read()`
77 time is discarded, returning the following frame instead. Again this
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Dvidioc-subdev-enum-frame-interval.rst1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
13 VIDIOC_SUBDEV_ENUM_FRAME_INTERVAL - Enumerate frame intervals
34 This ioctl lets applications enumerate available frame intervals on a
35 given sub-device pad. Frame intervals only makes sense for sub-devices
36 that can control the frame period on their own. This includes, for
39 For the common use case of image sensors, the frame intervals available
40 on the sub-device output pad depend on the frame format and size on the
42 when enumerating frame intervals.
44 To enumerate frame intervals applications initialize the ``index``,
49 EINVAL error code if one of the input fields is invalid. All frame
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Dext-ctrls-codec.rst1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
3 .. _codec-controls:
24 .. _mpeg-control-id:
27 -----------------
35 .. _v4l2-mpeg-stream-type:
40 enum v4l2_mpeg_stream_type -
41 The MPEG-1, -2 or -4 output stream type. One cannot assume anything
48 .. flat-table::
49 :header-rows: 0
50 :stub-columns: 0
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Dvidioc-g-parm.rst1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
13 VIDIOC_G_PARM - VIDIOC_S_PARM - Get or set streaming parameters
38 Applications can request a different frame interval. The capture or
39 output device will be reconfigured to support the requested frame
41 repeat frames to achieve the requested frame interval.
44 frame interval that is typically embedded in the encoded video stream.
46 Changing the frame interval shall never change the format. Changing the
47 format, on the other hand, may change the frame interval.
49 Further these ioctls can be used to determine the number of buffers used
63 .. flat-table:: struct v4l2_streamparm
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Dvidioc-subdev-g-frame-interval.rst1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
13 VIDIOC_SUBDEV_G_FRAME_INTERVAL - VIDIOC_SUBDEV_S_FRAME_INTERVAL - Get or set the frame interval on …
38 These ioctls are used to get and set the frame interval at specific
39 subdev pads in the image pipeline. The frame interval only makes sense
40 for sub-devices that can control the frame period on their own. This
41 includes, for instance, image sensors and TV tuners. Sub-devices that
42 don't support frame intervals must not implement these ioctls.
44 To retrieve the current frame interval applications set the ``pad``
47 the desired pad number as reported by the media controller API. When
51 To change the current frame interval applications set both the ``pad``
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Dext-ctrls-codec-stateless.rst1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
3 .. _codec-stateless-controls:
18 .. _codec-stateless-control-id:
23 .. _v4l2-codec-stateless-h264:
43 .. flat-table:: struct v4l2_ctrl_h264_sps
44 :header-rows: 0
45 :stub-columns: 0
48 * - __u8
49 - ``profile_idc``
50 -
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Dmetafmt-d4xx.rst1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
3 .. _v4l2-meta-fmt-d4xx:
15 Intel D4xx (D435, D455 and others) cameras include per-frame metadata in their UVC
27 per frame, therefore their headers cannot be larger than 255 bytes.
37 .. flat-table:: D4xx metadata
39 :header-rows: 1
40 :stub-columns: 0
42 * - **Field**
43 - **Description**
44 * - :cspan:`1` *Depth Control*
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Ddev-encoder.rst1 .. SPDX-License-Identifier: GPL-2.0 OR GFDL-1.1-no-invariants-or-later
6 Memory-to-Memory Stateful Video Encoder Interface
12 further post-processing by the client.
34 5. Single-planar API (see :ref:`planar-apis`) and applicable structures may be
35 used interchangeably with multi-planar API, unless specified otherwise,
47 Refer to :ref:`decoder-glossary`.
52 .. kernel-render:: DOT
65 qi -> Initialization [ label = "open()" ];
67 Initialization -> Encoding [ label = "Both queues streaming" ];
69 Encoding -> Drain [ label = "V4L2_ENC_CMD_STOP" ];
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Dvidioc-subdev-enum-frame-size.rst1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
13 VIDIOC_SUBDEV_ENUM_FRAME_SIZE - Enumerate media bus frame sizes
34 This ioctl allows applications to access the enumeration of frame sizes
35 supported by a sub-device on the specified pad
47 Therefore, to enumerate frame sizes allowed on the specified pad
54 A successful call will return with minimum and maximum frame sizes filled in.
59 Sub-devices that only support discrete frame sizes (such as most
60 sensors) will return one or more frame sizes with identical minimum and
64 supported. For instance, a scaler that uses a fixed-point scaling ratio
65 might not be able to produce every frame size between the minimum and
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Ddev-decoder.rst1 .. SPDX-License-Identifier: GPL-2.0
6 Memory-to-Memory Stateful Video Decoder Interface
9 A stateful video decoder takes complete chunks of the bytestream (e.g. Annex-B
34 5. Single-planar API (see :ref:`planar-apis`) and applicable structures may be
35 used interchangeably with multi-planar API, unless specified otherwise,
44 .. _decoder-glossary:
79 Good at sub-partitioning the picture into variable sized structures.
83 coded format includes a feature of frame reordering; for decoders,
97 raw frame available for reference in further decoding steps.
103 Instantaneous Decoder Refresh; a type of a keyframe in an H.264/HEVC-encoded
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/Documentation/userspace-api/media/drivers/
Dcamera-sensor.rst1 .. SPDX-License-Identifier: GPL-2.0
8 This section describes common practices for how the V4L2 sub-device interface is
13 Frame size
14 ----------
16 There are two distinct ways to configure the frame size produced by camera
23 processing pipeline as one or more sub-devices with different cropping and
33 they control based on user requests, are limited to a number of preset
34 configurations that combine a number of different parameters that on hardware
40 Frame interval configuration
41 ----------------------------
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Dnpcm-video.rst1 .. SPDX-License-Identifier: GPL-2.0
10 capture a frame from digital video input and compare two frames in memory, and
11 the ECE can compress the frame data into HEXTILE format.
13 Driver-specific Controls
14 ------------------------
21 - COMPLETE mode:
23 Capture the next complete frame into memory.
25 - DIFF mode:
27 Compare the incoming frame with the frame stored in memory, and updates the
28 differentiated frame in memory.
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/Documentation/fb/
Dapi.rst2 The Frame Buffer Device API
9 ---------------
11 This document describes the frame buffer API used by applications to interact
12 with frame buffer devices. In-kernel APIs between device drivers and the frame
15 Due to a lack of documentation in the original frame buffer API, drivers
22 ---------------
36 - FB_CAP_FOURCC
44 --------------------
46 Pixels are stored in memory in hardware-dependent formats. Applications need
48 frame buffer memory in the format expected by the hardware.
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Dframebuffer.rst2 The Frame Buffer Device
9 ---------------
11 The frame buffer device provides an abstraction for the graphics hardware. It
12 represents the frame buffer of some video hardware and allows application
13 software to access the graphics hardware through a well-defined interface, so
14 the software doesn't need to know anything about the low-level (hardware
22 --------------------------
24 From the user's point of view, the frame buffer device looks just like any
26 specifies the frame buffer number.
31 0 = /dev/fb0 First frame buffer
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/Documentation/devicetree/bindings/interrupt-controller/
Dmarvell,odmi-controller.txt4 Some Marvell SoCs have an On-Die Message Interrupt (ODMI) controller
5 which can be used by on-board peripheral for MSI interrupts.
9 - compatible : The value here should contain:
11 "marvell,ap806-odmi-controller", "marvell,odmi-controller".
13 - interrupt,controller : Identifies the node as an interrupt controller.
15 - msi-controller : Identifies the node as an MSI controller.
17 - marvell,odmi-frames : Number of ODMI frames available. Each frame
18 provides a number of events.
20 - reg : List of register definitions, one for each
21 ODMI frame.
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/Documentation/devicetree/bindings/soc/fsl/cpm_qe/
Dfsl,qe-tsa.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/fsl/cpm_qe/fsl,qe-tsa.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: PowerQUICC QE Time-slot assigner (TSA) controller
10 - Herve Codina <herve.codina@bootlin.com>
13 The TSA is the time-slot assigner that can be found on some PowerQUICC SoC.
14 Its purpose is to route some TDM time-slots to other internal serial
20 - enum:
21 - fsl,mpc8321-tsa
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Dfsl,cpm1-tsa.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/fsl/cpm_qe/fsl,cpm1-tsa.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: PowerQUICC CPM Time-slot assigner (TSA) controller
10 - Herve Codina <herve.codina@bootlin.com>
13 The TSA is the time-slot assigner that can be found on some PowerQUICC SoC.
14 Its purpose is to route some TDM time-slots to other internal serial
20 - enum:
21 - fsl,mpc885-tsa
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/Documentation/ABI/testing/
Dconfigfs-usb-gadget-uvc1 What: /config/usb-gadget/gadget/functions/uvc.name
13 What: /config/usb-gadget/gadget/functions/uvc.name/control
21 bInterfaceNumber USB interface number for this
27 What: /config/usb-gadget/gadget/functions/uvc.name/control/class
32 What: /config/usb-gadget/gadget/functions/uvc.name/control/class/ss
37 What: /config/usb-gadget/gadget/functions/uvc.name/control/class/fs
42 What: /config/usb-gadget/gadget/functions/uvc.name/control/terminal
47 What: /config/usb-gadget/gadget/functions/uvc.name/control/terminal/output
52 What: /config/usb-gadget/gadget/functions/uvc.name/control/terminal/output/default
66 bTerminalID a non-zero id of this terminal
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/Documentation/admin-guide/media/
Dmgb4.rst1 .. SPDX-License-Identifier: GPL-2.0
7 ---------------
13 There are two types of parameters - global / PCI card related, found under
23 | 0 - No module present
24 | 1 - FPDL3
25 | 2 - GMSL
28 Module version number. Zero in case of a missing module.
33 | 1 - FPDL3
34 | 2 - GMSL
37 Firmware version number.
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/Documentation/sound/soc/
Dclocking.rst10 ------------
13 or SYSCLK). This audio master clock can be derived from a number of sources
23 ----------
28 The DAI also has a frame clock to signal the start of each audio frame. This
29 clock is sometimes referred to as LRC (left right clock) or FRAME. This clock
32 Bit Clock can be generated as follows:-
34 - BCLK = MCLK / x, or
35 - BCLK = LRC * x, or
36 - BCLK = LRC * Channels * Word Size
40 rate, number of channels and word size) to save on power.
/Documentation/networking/
Dpacket_mmap.rst1 .. SPDX-License-Identifier: GPL-2.0
22 - Ulisses Alonso Camaró <uaca@i.hate.spam.alumni.uv.es>
23 - Johann Baudy
67 [setup] socket() -------> creation of the capture socket
68 setsockopt() ---> allocation of the circular buffer (ring)
70 mmap() ---------> mapping of the allocated buffer to the
73 [capture] poll() ---------> to wait for incoming packets
75 [shutdown] close() --------> destruction of the capture socket and
88 supported and a link level pseudo-header is provided
107 [setup] socket() -------> creation of the transmission socket
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Doa-tc6-framework.rst1 .. SPDX-License-Identifier: GPL-2.0+
4 OPEN Alliance 10BASE-T1x MAC-PHY Serial Interface (TC6) Framework Support
8 ------------
11 single pair of conductors. The 10BASE-T1L (Clause 146) is a long reach
12 PHY supporting full duplex point-to-point operation over 1 km of single
13 balanced pair of conductors. The 10BASE-T1S (Clause 147) is a short reach
14 PHY supporting full / half duplex point-to-point operation over 15 m of
21 works in conjunction with the 10BASE-T1S PHY operating in multidrop mode.
23 The aforementioned PHYs are intended to cover the low-speed / low-cost
24 applications in industrial and automotive environment. The large number
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