Searched +full:full +full:- +full:speed (Results 1 – 25 of 177) sorted by relevance
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| /Documentation/ABI/testing/ |
| D | sysfs-bus-pci-drivers-ehci_hcd | 7 PCI-based EHCI USB controllers (i.e., high-speed USB-2.0
9 "companion" full/low-speed USB-1.1 controllers. When a
10 high-speed device is plugged in, the connection is routed
11 to the EHCI controller; when a full- or low-speed device
15 Sometimes you want to force a high-speed device to connect
16 at full speed, which can be accomplished by forcing the
23 For example: To force the high-speed device attached to
24 port 4 on bus 2 to run at full speed::
28 To return the port to high-speed operation::
30 echo -4 >/sys/bus/usb/devices/usb2/../companion
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| D | sysfs-class-led-trigger-netdev | 4 Contact: linux-leds@vger.kernel.org
11 Contact: linux-leds@vger.kernel.org
24 Contact: linux-leds@vger.kernel.org
38 Contact: linux-leds@vger.kernel.org
53 Contact: linux-leds@vger.kernel.org
68 Contact: linux-leds@vger.kernel.org
81 Contact: linux-leds@vger.kernel.org
83 Signal the link speed state of 10Mbps of the named network device.
88 speed of 10MBps of the named network device.
91 Present only if the named network device supports 10Mbps link speed.
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| /Documentation/hwmon/ |
| D | dme1737.rst | 18 Addresses scanned: none, address read from Super-I/O config space
34 Addresses scanned: none, address read from Super-I/O config space
43 -----------------
52 Include non-standard LPC addresses 0x162e and 0x164e
55 - VIA EPIA SN18000
59 -----------
63 and SCH5127 Super-I/O chips. These chips feature monitoring of 3 temp sensors
64 temp[1-3] (2 remote diodes and 1 internal), 8 voltages in[0-7] (7 external and
65 1 internal) and up to 6 fan speeds fan[1-6]. Additionally, the chips implement
66 up to 5 PWM outputs pwm[1-3,5-6] for controlling fan speeds both manually and
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| D | g762.rst | 4 The GMT G762 Fan Speed PWM Controller is connected directly to a fan
5 and performs closed-loop or open-loop control of the fan speed. Two
6 modes - PWM or DC - are supported by the device.
9 http://natisbad.org/NAS/ref/GMT_EDS-762_763-080710-0.2.pdf. sysfs
10 bindings are described in Documentation/hwmon/sysfs-interface.rst.
25 set desired fan speed. This only makes sense in closed-loop
26 fan speed control (i.e. when pwm1_enable is set to 2).
44 in closed-loop control mode, if fan RPM value is 25% out
49 set current fan speed control mode i.e. 1 for manual fan
50 speed control (open-loop) via pwm1 described below, 2 for
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| D | vt1211.rst | 10 Addresses scanned: none, address read from Super-I/O config space
24 -----------------
29 configuration for channels 1-5.
30 Legal values are in the range of 0-31. Bit 0 maps to
47 -----------
49 The VIA VT1211 Super-I/O chip includes complete hardware monitoring
52 implements 5 universal input channels (UCH1-5) that can be individually
60 connected to the PWM outputs of the VT1211 :-().
80 ------------------
82 Voltages are sampled by an 8-bit ADC with a LSB of ~10mV. The supported input
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| D | sch5627.rst | 18 -----------
24 affect the speed of each fan. Setting pwmX_auto_channels_temp to 0 forces
25 the corresponding fan to full speed until another value is written.
38 Controlling fan speed
39 ---------------------
41 The SCH5627 allows for partially controlling the fan speed. If a temperature
42 channel excedes tempX_max, all fans are forced to maximum speed. The same is not
45 In which way the value of fanX_min affects the fan speed is currently unknown.
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| D | adm1026.rst | 16 - Philip Pokorny <ppokorny@penguincomputing.com> for Penguin Computing
17 - Justin Thiessen <jthiessen@penguincomputing.com>
20 -----------------
23 List of GPIO pins (0-16) to program as inputs
26 List of GPIO pins (0-16) to program as outputs
29 List of GPIO pins (0-16) to program as inverted
32 List of GPIO pins (0-16) to program as normal/non-inverted
35 List of GPIO pins (0-7) to program as fan tachs
39 -----------
45 16 general purpose digital I/O lines, eight (8) fan speed sensors (8-bit),
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| D | adt7462.rst | 17 -----------
21 This chip is a bit of a beast. It has 8 counters for measuring fan speed. It
28 that allows fan speed to be adjusted automatically based on any of the three
34 Each of the measured inputs (voltage, temperature, fan speed) has
43 ----------------
45 The ADT7462 have a 10-bit ADC and can therefore measure temperatures
55 -------------------
62 * pwm#_auto_point2_pwm and temp#_auto_point2_temp -
64 - point1: Set the pwm speed at a lower temperature bound.
65 - point2: Set the pwm speed at a higher temperature bound.
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| D | w83792d.rst | 10 Addresses scanned: I2C 0x2c - 0x2f
19 -----------------
35 -----------
42 parameter; this will put it into a more well-behaved state first.
44 The driver implements three temperature sensors, seven fan rotation speed
48 The driver also implements up to seven fan control outputs: pwm1-7. Pwm1-7
53 Automatic fan control mode is possible only for fan1-fan3.
55 For all pwmX outputs, a value of 0 means minimum fan speed and a value of
56 255 means maximum fan speed.
64 triggered if the rotation speed has dropped below a programmable limit. Fan
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| D | adt7470.rst | 17 -----------
22 The ADT7470 uses the 2-wire interface compatible with the SMBus 2.0
24 external temperatures. It has four (4) 16-bit counters for measuring fan speed.
25 There are four (4) PWM outputs that can be used to control fan speed.
28 that allows fan speed to be adjusted automatically based on any of the ten
34 Each of the measured inputs (temperature, fan speed) has corresponding high/low
40 automatic fan pwm control to set the fan speed. The driver will not read the
45 ----------------
47 The ADT7470 has a 8-bit ADC and is capable of measuring temperatures with 1
54 -------------------
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| D | nct6775.rst | 19 * Nuvoton NCT5572D/NCT6771F/NCT6772F/NCT6775F/W83677HG-I
83 * Nuvoton NCT6796D-S/NCT6799D-R
93 Guenter Roeck <linux@roeck-us.net>
96 -----------
106 There are 4 to 5 fan rotation speed sensors, 8 to 15 analog voltage sensors,
120 triggered if the rotation speed has dropped below a programmable limit. On
123 do not have a fan speed divider. The driver sets the most suitable fan divisor
124 itself; specifically, it increases the divider value each time a fan speed
125 reading returns an invalid value, and it reduces it if the fan speed reading
138 The mode works for fan1-fan5.
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| /Documentation/usb/ |
| D | ehci.rst | 5 27-Dec-2002
7 The EHCI driver is used to talk to high speed USB 2.0 devices using
8 USB 2.0-capable host controller hardware. The USB 2.0 standard is
11 - "High Speed" 480 Mbit/sec (60 MByte/sec)
12 - "Full Speed" 12 Mbit/sec (1.5 MByte/sec)
13 - "Low Speed" 1.5 Mbit/sec
15 USB 1.1 only addressed full speed and low speed. High speed devices
23 (TT) in the hub, which turns low or full speed transactions into
24 high speed "split transactions" that don't waste transfer bandwidth.
31 While usb-storage devices have been available since mid-2001 (working
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| /Documentation/networking/device_drivers/ethernet/intel/ |
| D | e1000.rst | 1 .. SPDX-License-Identifier: GPL-2.0+
8 Copyright(c) 1999 - 2013 Intel Corporation.
13 - Identifying Your Adapter
14 - Command Line Parameters
15 - Speed and Duplex Configuration
16 - Additional Configurations
17 - Support
40 For more information about the AutoNeg, Duplex, and Speed
41 parameters, see the "Speed and Duplex Configuration" section in
50 -------
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| /Documentation/devicetree/bindings/usb/ |
| D | usb.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Greg Kroah-Hartman <gregkh@linuxfoundation.org>
22 phy-names:
26 usb-phy:
27 $ref: /schemas/types.yaml#/definitions/phandle-array
38 UTMI+ PHY with an 8- or 16-bit interface if UTMI+ is selected, UTMI+ low
40 serial is specified and High-Speed Inter-Chip feature if HSIC is
46 maximum-speed:
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| D | cdns,usb3.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Cadence USBSS-DRD controller
10 - Pawel Laszczak <pawell@cadence.com>
18 - description: OTG controller registers
19 - description: XHCI Host controller registers
20 - description: DEVICE controller registers
22 reg-names:
24 - const: otg
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| /Documentation/devicetree/bindings/sound/ |
| D | st,sta350.txt | 7 - compatible: "st,sta350"
8 - reg: the I2C address of the device for I2C
9 - reset-gpios: a GPIO spec for the reset pin. If specified, it will be
12 - power-down-gpios: a GPIO spec for the power down pin. If specified,
16 - vdd-dig-supply: regulator spec, providing 3.3V
17 - vdd-pll-supply: regulator spec, providing 3.3V
18 - vcc-supply: regulator spec, providing 5V - 26V
22 - st,output-conf: number, Selects the output configuration:
23 0: 2-channel (full-bridge) power, 2-channel data-out
24 1: 2 (half-bridge). 1 (full-bridge) on-board power
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| D | st,sta32x.txt | 7 - compatible: "st,sta32x"
8 - reg: the I2C address of the device for I2C
9 - reset-gpios: a GPIO spec for the reset pin. If specified, it will be
12 - power-down-gpios: a GPIO spec for the power down pin. If specified,
16 - Vdda-supply: regulator spec, providing 3.3V
17 - Vdd3-supply: regulator spec, providing 3.3V
18 - Vcc-supply: regulator spec, providing 5V - 26V
22 - clocks, clock-names: Clock specifier for XTI input clock.
24 and disabled when it is removed. The 'clock-names' must be set to 'xti'.
26 - st,output-conf: number, Selects the output configuration:
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| /Documentation/devicetree/bindings/soc/fsl/cpm_qe/qe/ |
| D | usb.txt | 4 - compatible : should be "fsl,<chip>-qe-usb", "fsl,mpc8323-qe-usb".
5 - reg : the first two cells should contain usb registers location and
8 - interrupts : should contain USB interrupt.
9 - fsl,fullspeed-clock : specifies the full speed USB clock source:
11 "brg1" through "brg16": clock source is BRG1-BRG16, respectively
12 "clk1" through "clk24": clock source is CLK1-CLK24, respectively
13 - fsl,lowspeed-clock : specifies the low speed USB clock source:
15 "brg1" through "brg16": clock source is BRG1-BRG16, respectively
16 "clk1" through "clk24": clock source is CLK1-CLK24, respectively
17 - hub-power-budget : USB power budget for the root hub, in mA.
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| /Documentation/networking/device_drivers/can/ |
| D | can327.rst | 1 .. SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
7 --------
14 -----------
26 -------------
29 into full fledged (as far as possible) CAN interfaces.
33 order to fake full-duplex operation.
36 enough to implement simple request-response protocols (such as OBD II),
50 -----------
59 ----------------------------------
68 --debug \
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| /Documentation/devicetree/bindings/net/dsa/ |
| D | microchip,lan937x.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - UNGLinuxDriver@microchip.com
13 - $ref: dsa.yaml#/$defs/ethernet-ports
18 - microchip,lan9370
19 - microchip,lan9371
20 - microchip,lan9372
21 - microchip,lan9373
22 - microchip,lan9374
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| D | microchip,ksz.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Marek Vasut <marex@denx.de>
11 - Woojung Huh <Woojung.Huh@microchip.com>
14 - $ref: /schemas/spi/spi-peripheral-props.yaml#
21 - microchip,ksz8765
22 - microchip,ksz8794
23 - microchip,ksz8795
24 - microchip,ksz8863
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| /Documentation/devicetree/bindings/ |
| D | xilinx.txt | 10 Each IP-core has a set of parameters which the FPGA designer can use to
20 properties of the device node. In general, device nodes for IP-cores
23 (name): (generic-name)@(base-address) {
24 compatible = "xlnx,(ip-core-name)-(HW_VER)"
27 interrupt-parent = <&interrupt-controller-phandle>;
29 xlnx,(parameter1) = "(string-value)";
30 xlnx,(parameter2) = <(int-value)>;
33 (generic-name): an open firmware-style name that describes the
36 (ip-core-name): the name of the ip block (given after the BEGIN
38 and all underscores '_' converted to dashes '-'.
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| /Documentation/devicetree/bindings/mmc/ |
| D | mmc-controller.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/mmc/mmc-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Ulf Hansson <ulf.hansson@linaro.org>
25 "#address-cells":
30 "#size-cells":
37 broken-cd:
42 cd-gpios:
47 non-removable:
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| /Documentation/devicetree/bindings/net/ |
| D | ethernet-controller.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/net/ethernet-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - David S. Miller <davem@davemloft.net>
19 local-mac-address:
22 $ref: /schemas/types.yaml#/definitions/uint8-array
26 mac-address:
31 local-mac-address property.
32 $ref: /schemas/types.yaml#/definitions/uint8-array
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| /Documentation/devicetree/bindings/phy/ |
| D | qcom,usb-hs-28nm.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/qcom,usb-hs-28nm.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Synopsys DesignWare Core 28nm High-Speed PHY
10 - Bryan O'Donoghue <bryan.odonoghue@linaro.org>
13 Qualcomm Low-Speed, Full-Speed, Hi-Speed 28nm USB PHY
18 - qcom,usb-hs-28nm-femtophy
23 "#phy-cells":
28 - description: rpmcc ref clock
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