Searched full:gate (Results 1 – 25 of 115) sorted by relevance
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| /Documentation/devicetree/bindings/clock/ti/ |
| D | gate.txt | 1 Binding for Texas Instruments gate clock.
4 quite much similar to the basic gate-clock [2], however,
11 [2] Documentation/devicetree/bindings/clock/gpio-gate-clock.yaml
16 "ti,gate-clock" - basic gate clock
17 "ti,wait-gate-clock" - gate clock which waits until clock is active before
19 "ti,dss-gate-clock" - gate clock with DSS specific hardware handling
20 "ti,am35xx-gate-clock" - gate clock with AM35xx specific hardware handling
21 "ti,clkdm-gate-clock" - clockdomain gate clock, which derives its functional
24 "ti,hsdiv-gate-clock" - gate clock with OMAP36xx specific hardware handling,
26 "ti,composite-gate-clock" - composite gate clock, to be part of composite
[all …]
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| D | interface.txt | 4 quite much similar to the basic gate-clock [2], however,
6 companion clock finding (match corresponding functional gate
10 [2] Documentation/devicetree/bindings/clock/gpio-gate-clock.yaml
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| /Documentation/devicetree/bindings/clock/ |
| D | sprd,sc9860-clk.yaml | 17 - sprd,sc9860-agcp-gate
19 - sprd,sc9860-aon-gate
21 - sprd,sc9860-apahb-gate
22 - sprd,sc9860-apapb-gate
25 - sprd,sc9860-cam-gate
27 - sprd,sc9860-disp-gate
30 - sprd,sc9860-pmu-gate
32 - sprd,sc9860-vsp-gate
61 - sprd,sc9860-agcp-gate
62 - sprd,sc9860-aon-gate
[all …]
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| D | sprd,ums512-clk.yaml | 18 - sprd,ums512-apahb-gate
21 - sprd,ums512-pmu-gate
26 - sprd,ums512-aon-gate
27 - sprd,ums512-audcpapb-gate
28 - sprd,ums512-audcpahb-gate
31 - sprd,ums512-mm-gate-clk
32 - sprd,ums512-apapb-gate
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| D | sprd,sc9863a-clk.yaml | 23 - sprd,sc9863a-apahb-gate
24 - sprd,sc9863a-pmu-gate
25 - sprd,sc9863a-aonapb-gate
30 - sprd,sc9863a-mm-gate
32 - sprd,sc9863a-apapb-gate
95 apahb_gate: apahb-gate@0 {
96 compatible = "sprd,sc9863a-apahb-gate";
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| D | altr_socfpga.txt | 12 "altr,socfpga-gate-clk" - Clocks that directly feed peripherals and
22 - clk-gate : For "socfpga-gate-clk", clk-gate contains the gating register
24 - div-reg : For "socfpga-gate-clk" and "socfpga-periph-clock", div-reg contains
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| D | gpio-gate-clock.yaml | 4 $id: http://devicetree.org/schemas/clock/gpio-gate-clock.yaml#
7 title: Simple GPIO clock gate
14 const: gpio-gate-clock
38 compatible = "gpio-gate-clock";
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| D | sophgo,sg2042-rpgate.yaml | 7 title: Sophgo SG2042 Gate Clock Generator for RP(riscv processors) subsystem
21 - description: Gate clock for RP subsystem
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| D | mediatek,mt8186-clock.yaml | 18 clock gate
20 The devices provide clock gate control in different IP blocks.
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| D | mediatek,mt8186-sys-clock.yaml | 18 clock gate
22 The infracfg_ao provides clock gate in peripheral and infrastructure IP blocks.
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| D | mediatek,mt8188-sys-clock.yaml | 18 clock gate
22 The infracfg_ao provides clock gate in peripheral and infrastructure IP blocks.
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| /Documentation/devicetree/bindings/i2c/ |
| D | i2c-gate.yaml | 4 $id: http://devicetree.org/schemas/i2c/i2c-gate.yaml#
7 title: Common i2c gate properties
13 An i2c gate is useful to e.g. reduce the digital noise for RF tuners connected
15 some kind of operation to access the i2c bus past the arbitrator/gate, but
24 const: i2c-gate
30 i2c-gate {
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| /Documentation/devicetree/bindings/dma/ |
| D | cirrus,ep9301-dma-m2p.yaml | 43 - description: m2p0 channel gate clock
44 - description: m2p1 channel gate clock
45 - description: m2p2 channel gate clock
46 - description: m2p3 channel gate clock
47 - description: m2p4 channel gate clock
48 - description: m2p5 channel gate clock
49 - description: m2p6 channel gate clock
50 - description: m2p7 channel gate clock
51 - description: m2p8 channel gate clock
52 - description: m2p9 channel gate clock
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| /Documentation/devicetree/bindings/mfd/ |
| D | omap-usb-host.txt | 48 * "usb_host_hs_utmi_p1_clk" - Port 1 UTMI clock gate.
49 * "usb_host_hs_utmi_p2_clk" - Port 2 UTMI clock gate.
50 * "usb_host_hs_utmi_p3_clk" - Port 3 UTMI clock gate.
51 * "usb_host_hs_hsic480m_p1_clk" - Port 1 480MHz HSIC clock gate.
52 * "usb_host_hs_hsic480m_p2_clk" - Port 2 480MHz HSIC clock gate.
53 * "usb_host_hs_hsic480m_p3_clk" - Port 3 480MHz HSIC clock gate.
54 * "usb_host_hs_hsic60m_p1_clk" - Port 1 60MHz HSIC clock gate.
55 * "usb_host_hs_hsic60m_p2_clk" - Port 2 60MHz HSIC clock gate.
56 * "usb_host_hs_hsic60m_p3_clk" - Port 3 60MHz HSIC clock gate.
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| /Documentation/devicetree/bindings/display/samsung/ |
| D | samsung,exynos-hdmi.yaml | 116 - description: Gate of HDMI IP APB bus.
117 - description: Gate of HDMI-PHY IP APB bus.
118 - description: Gate of HDMI TMDS clock.
119 - description: Gate of HDMI pixel clock.
128 - description: Gate of HDMI SPDIF clock.
147 - description: Gate of HDMI IP bus clock.
148 - description: Gate of HDMI special clock.
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| /Documentation/devicetree/bindings/input/touchscreen/ |
| D | toradex,vf50-touchscreen.yaml | 27 description: FET gate driver for input of X+
30 description: FET gate driver for input of X-
33 description: FET gate driver for input of Y+
36 description: FET gate driver for input of Y-
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| /Documentation/devicetree/bindings/iio/imu/ |
| D | invensense,mpu6050.yaml | 56 i2c-gate:
60 These devices also support an auxiliary i2c bus via an i2c-gate.
76 i2c-gate: false
106 i2c-gate {
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| /Documentation/devicetree/bindings/pci/ |
| D | hisilicon-histb-pcie.txt | 24 "aux": auxiliary gate clock;
25 "pipe": pipe gate clock;
26 "sys": sys gate clock;
27 "bus": bus gate clock.
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| /Documentation/devicetree/bindings/mmc/ |
| D | mtk-sd.yaml | 201 - description: independent source clock gate
221 - description: independent source clock gate
254 - description: independent source clock gate
256 - description: msdc subsys clock gate
279 - description: independent source clock gate
299 - description: independent source clock gate
300 - description: msdc subsys clock gate
301 - description: peripheral bus clock gate
302 - description: AXI bus clock gate
303 - description: AHB bus clock gate
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| /Documentation/devicetree/bindings/iio/gyroscope/ |
| D | invensense,mpu3050.yaml | 30 i2c-gate:
37 i2c-gate subnode.
59 i2c-gate {
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| /Documentation/devicetree/bindings/phy/ |
| D | samsung,usb3-drd-phy.yaml | 115 - description: Gate of main PHY clock
116 - description: Gate of PHY reference clock
117 - description: Gate of control interface AXI clock
118 - description: Gate of control interface APB clock
119 - description: Gate of SCL APB clock
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| /Documentation/devicetree/bindings/media/i2c/ |
| D | maxim,max96717.yaml | 86 i2c-gate:
87 $ref: /schemas/i2c/i2c-gate.yaml
91 incoming GMSL2 link. Therefore, it supports an i2c-gate
136 i2c-gate {
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| D | maxim,max96714.yaml | 87 i2c-gate:
88 $ref: /schemas/i2c/i2c-gate.yaml
92 incoming I2C bus over the GMSL2 link. Therefore it supports an i2c-gate
139 i2c-gate {
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| /Documentation/devicetree/bindings/iommu/ |
| D | sprd,iommu.yaml | 31 Reference to a gate clock phandle, since access to some of IOMMUs are
32 controlled by gate clock, but this is not required.
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| /Documentation/devicetree/bindings/soc/sprd/ |
| D | sprd,sc9863a-glbregs.yaml | 48 apahb_gate: apahb-gate@0 {
49 compatible = "sprd,sc9863a-apahb-gate";
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