Searched full:gates (Results 1 – 25 of 26) sorted by relevance
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| /Documentation/devicetree/bindings/clock/ |
| D | allwinner,sun4i-a10-gates-clk.yaml | 4 $id: http://devicetree.org/schemas/clock/allwinner,sun4i-a10-gates-clk.yaml#
7 title: Allwinner A10 Bus Gates Clock
24 - const: allwinner,sun4i-a10-gates-clk
25 - const: allwinner,sun4i-a10-axi-gates-clk
26 - const: allwinner,sun4i-a10-ahb-gates-clk
27 - const: allwinner,sun5i-a10s-ahb-gates-clk
28 - const: allwinner,sun5i-a13-ahb-gates-clk
29 - const: allwinner,sun7i-a20-ahb-gates-clk
30 - const: allwinner,sun6i-a31-ahb1-gates-clk
31 - const: allwinner,sun8i-a23-ahb1-gates-clk
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| D | allwinner,sun8i-h3-bus-gates-clk.yaml | 4 $id: http://devicetree.org/schemas/clock/allwinner,sun8i-h3-bus-gates-clk.yaml#
7 title: Allwinner A10 Bus Gates Clock
23 const: allwinner,sun8i-h3-bus-gates-clk
59 compatible = "allwinner,sun8i-h3-bus-gates-clk";
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| D | renesas,cpg-mstp-clocks.yaml | 13 The Clock Pulse Generator (CPG) can gate SoC device clocks. The gates are
14 organized in groups of up to 32 gates.
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| D | st,nomadik.txt | 7 PLLs and clock gates.
34 HCLK nodes: these represent the clock gates on individual
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| D | alphascale,acc.txt | 4 clock source, setting dividers and clock gates.
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| D | microchip,mpfs-clkcfg.yaml | 14 which gates and enables all peripheral clocks.
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| D | ingenic,cgu.yaml | 11 typically includes a variety of PLLs, multiplexers, dividers & gates in order
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| D | imx8qxp-lpcg.yaml | 14 model to control the clock gates for the peripherals. An LPCG module
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| D | pistachio-clock.txt | 103 gates for the external clocks "audio_clk_in" and "enet_clk_in".
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| /Documentation/devicetree/bindings/i2c/ |
| D | i2c-gate.yaml | 14 to the i2c bus. Gates are similar to arbitrators in that you need to perform
16 there are no competing masters to consider for gates and therefore there is
17 no arbitration happening for gates.
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| /Documentation/devicetree/bindings/mfd/ |
| D | allwinner,sun6i-a31-prcm.yaml | 32 - allwinner,sun6i-a31-apb0-gates-clk
98 const: allwinner,sun6i-a31-apb0-gates-clk
199 apb0_gates: apb0-gates-clk {
200 compatible = "allwinner,sun6i-a31-apb0-gates-clk";
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| D | allwinner,sun8i-a23-prcm.yaml | 32 - allwinner,sun8i-a23-apb0-gates-clk
75 const: allwinner,sun8i-a23-apb0-gates-clk
150 compatible = "allwinner,sun8i-a23-apb0-gates-clk";
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| /Documentation/driver-api/nfc/ |
| D | nfc-hci.rst | 38 support proprietary gates. This is the reason why the driver will pass a list
39 of proprietary gates that must be part of the session. HCI will ensure all
40 those gates have pipes connected when the hci device is set up.
41 In case the chip supports pre-opened gates and pseudo-static pipes, the driver
44 HCI Gates and Pipes
49 implementation, pipes are totally hidden. The public API only knows gates.
50 This is consistent with the driver need to send commands to proprietary gates
96 mode. This must be implemented only if the hardware uses proprietary gates or a
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| /Documentation/driver-api/fpga/ |
| D | intro.rst | 38 actual hard hardware that gates a bus to a CPU or a soft ("freeze")
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| /Documentation/devicetree/bindings/clock/ti/davinci/ |
| D | pll.txt | 4 to the PLL itself, this controller also contains bypasses, gates, dividers,
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| D | da8xx-cfgchip.txt | 5 gates. This document describes the bindings for those clocks.
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| /Documentation/devicetree/bindings/clock/ti/ |
| D | gate.txt | 41 gates the clock and clearing the bit ungates the clock.
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| /Documentation/devicetree/bindings/display/ |
| D | allwinner,sun8i-r40-tcon-top.yaml | 17 encoder clock source and contains additional TV TCON and DSI gates.
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| /Documentation/admin-guide/LSM/ |
| D | SafeSetID.rst | 4 SafeSetID is an LSM module that gates the setid family of syscalls to restrict
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| /Documentation/hwmon/ |
| D | adm9240.rst | 95 Two fan tacho inputs are provided, the ADM9240 gates an internal 22.5kHz
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| /Documentation/networking/dsa/ |
| D | sja1105.rst | 136 and the gates for all other traffic classes are open for 400 us::
274 fact that no two gate actions (either tc-gate or tc-taprio gates) may fire at
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| /Documentation/i2c/ |
| D | i2c-topology.rst | 19 Several types of hardware components such as I2C muxes, I2C gates and I2C
113 gates/muxes, i.e. something that closes automatically after a given
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| /Documentation/virt/kvm/devices/ |
| D | vm.rst | 375 guest. The SMCCC filter gates the in-kernel emulation of SMCCC calls
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| /Documentation/accel/qaic/ |
| D | aic100.rst | 369 presync, which gates the DMA transfer. Only one presync is
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| /Documentation/driver-api/ |
| D | vfio.rst | 299 VFIO_DEVICE_BIND_IOMMUFD ioctl, which gates full device access.
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