Searched full:gating (Results 1 – 25 of 43) sorted by relevance
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| /Documentation/devicetree/bindings/clock/ |
| D | mvebu-gated-clock.txt | 7 corresponding clock gating control bit in HW to ease manual clock
177 "marvell,armada-370-gating-clock" - for Armada 370 SoC clock gating
178 "marvell,armada-375-gating-clock" - for Armada 375 SoC clock gating
179 "marvell,armada-380-gating-clock" - for Armada 380/385 SoC clock gating
180 "marvell,armada-390-gating-clock" - for Armada 39x SoC clock gating
181 "marvell,armada-xp-gating-clock" - for Armada XP SoC clock gating
182 "marvell,mv98dx3236-gating-clock" - for 98dx3236 SoC clock gating
183 "marvell,dove-gating-clock" - for Dove SoC clock gating
184 "marvell,kirkwood-gating-clock" - for Kirkwood SoC clock gating
185 - reg : shall be the register address of the Clock Gating Control register
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| D | imx8qxp-lpcg.yaml | 7 title: NXP i.MX8QXP LPCG (Low-Power Clock Gating) Clock
17 This level of clock gating is provided after the clocks are generated
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| D | brcm,bcm2835-aux-clock.txt | 7 area controlling clock gating to the peripherals, and providing an IRQ
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| D | imx8ulp-pcc-clock.yaml | 15 software reset, clock selection, optional division and clock gating mode
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| D | lpc1850-creg-clk.txt | 5 32 kHz oscillator driver with power up/down and clock gating. Next
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| D | altr_socfpga.txt | 22 - clk-gate : For "socfpga-gate-clk", clk-gate contains the gating register
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| D | imx8mp-audiomix.yaml | 13 NXP i.MX8M Plus AudioMIX is dedicated clock muxing and gating IP
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| D | nvidia,tegra20-car.yaml | 14 The Clock and Reset (CAR) is the HW module responsible for muxing and gating
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| D | nvidia,tegra124-car.yaml | 14 The Clock and Reset (CAR) is the HW module responsible for muxing and gating
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| D | imx7ulp-scg-clock.yaml | 33 clock gating mode.
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| D | imx7ulp-pcc-clock.yaml | 29 optional division and clock gating mode for peripherals in their
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| D | renesas,emev2-smu.yaml | 75 Clock gating node shown as "Clock stop processing block" in the
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| /Documentation/devicetree/bindings/power/ |
| D | fsl,imx-gpc.yaml | 14 counters and Power Gating Control (PGC).
18 described as subnodes of the power gating controller 'pgc' node of the GPC.
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| D | fsl,imx-gpcv2.yaml | 13 The i.MX7S/D General Power Control (GPC) block contains Power Gating
19 described as subnodes of the power gating controller 'pgc' node.
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| D | power_domain.txt | 4 used for power gating of selected IP blocks for power saving by reduced leakage
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| /Documentation/devicetree/bindings/arm/marvell/ |
| D | kirkwood.txt | 13 where the "powersave" clock is a gating clock used to switch the CPU
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| /Documentation/devicetree/bindings/memory-controllers/ |
| D | rockchip,rk3399-dmc.yaml | 79 Defines the memory self-refresh and controller clock gating idle period.
81 arg gating started if bus is idle for sr_mc_gate_idle*1024 DFI clock
300 Defines the memory self-refresh and controller clock gating idle period in nanoseconds.
302 arg gating started if bus is idle for sr_mc_gate_idle nanoseconds.
330 Defines the self-refresh and memory-controller clock gating disable
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| /Documentation/devicetree/bindings/clock/ti/ |
| D | composite.txt | 11 a gating function which can be used to enable and disable the output
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| D | dpll.txt | 54 - ti,low-power-stop : DPLL supports low power stop mode, gating output
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| /Documentation/arch/arm/sunxi/ |
| D | clocks.rst | 11 A: The 24MHz oscillator allows gating to save power. Indeed, if gated
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| /Documentation/devicetree/bindings/soc/imx/ |
| D | fsl,imx93-src.yaml | 19 - Responsible for power gating of MIXs (Slices) and their memory
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| /Documentation/devicetree/bindings/clock/ti/davinci/ |
| D | psc.txt | 3 The PSC provides power management, clock gating and reset functionality. It is
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| /Documentation/devicetree/bindings/serial/ |
| D | amlogic,meson-uart.yaml | 19 is active since power-on and does not need any clock gating and is usable
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| /Documentation/devicetree/bindings/cache/ |
| D | l2c2x0.yaml | 198 arm,dynamic-clock-gating:
200 L2 dynamic clock gating. Value: <0> (forcibly
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| /Documentation/driver-api/ |
| D | clk.rst | 17 gating, rate adjustment, muxing or other operations. This framework is
119 knowledge about which register and bit controls this clk's gating.
252 Disabling clock gating of unused clocks
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