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/Documentation/gpu/
Ddrm-mm.rst12 (TTM) and Graphics Execution Manager (GEM). TTM was the first DRM memory
20 GEM started as an Intel-sponsored project in reaction to TTM's
22 providing a solution to every graphics memory-related problems, GEM
24 share it. GEM has simpler initialization and execution requirements than
79 The Graphics Execution Manager (GEM)
82 The GEM design approach has resulted in a memory manager that doesn't
84 userspace or kernel API. GEM exposes a set of standard memory-related
89 The GEM userspace API is described in the `GEM - the Graphics Execution
91 slightly outdated, the document provides a good overview of the GEM API
93 as part of the common GEM API, are currently implemented using
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Ddrm-vm-bind-locking.rst34 a GEM object or anonymous or page-cache pages mapped also into the CPU
36 * ``gpu_vm_bo``: Abstracts the association of a GEM object and
37 a VM. The GEM object maintains a list of gpu_vm_bos, where each gpu_vm_bo
50 gpu_vm or a GEM object. The dma_resv contains an array / list
63 * ``local object``: A GEM object which is only mapped within a
64 single VM. Local GEM objects share the gpu_vm's dma_resv.
65 * ``external object``: a.k.a shared object: A GEM object which may be shared
72 One of the benefits of VM_BIND is that local GEM objects share the gpu_vm's
74 number of local GEM objects, only one lock is needed to make the exec
98 GEM objects.
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Di915.rst14 and the GEM parts of the driver.
270 This sections covers all things related to the GEM implementation in the
299 is encapsulated within GEM buffer objects (usually created with the ioctl
301 to create will also list all GEM buffer objects that the batchbuffer reads
303 `GEM BO Management Implementation Details`_.
331 submits a batchbuffer, the kernel walks the list of GEM buffer objects
333 each such GEM buffer object resident but it is also present in the
334 (PP)GTT. If the GEM buffer object is not yet placed in the (PP)GTT,
337 the GPU address when a GEM BO is assigned a GPU address and the kernel
338 might evict a different GEM BO from the (PP)GTT to make address room
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Dtegra.rst139 GEM buffers, access and control syncpoints as well as submit command streams
142 GEM Buffers
145 The ``DRM_IOCTL_TEGRA_GEM_CREATE`` IOCTL is used to create a GEM buffer object
149 After a GEM buffer object has been created, its memory can be mapped by an
176 writes commands into the memory backing a GEM buffer object and passes these
Dvc4.rst79 This section covers the GEM implementation in the vc4 driver.
85 :doc: VC4 GEM BO management support
Dv3d.rst12 :doc: V3D GEM BO management support
Ddrm-internals.rst119 Table Manager (TTM) and the Graphics Execution Manager (GEM). This
120 document describes the use of the GEM memory manager only. See ? for
Dtodo.rst35 All GEM based drivers should be using drm_gem_create_mmap_offset() instead.
176 Get rid of dev->struct_mutex from GEM drivers
181 serializing GEM buffer object destruction. Which unfortunately means drivers
185 Core GEM doesn't have a need for ``struct_mutex`` any more since kernel 4.8,
186 and there's a GEM object ``free`` callback for any drivers which are
310 gem objects (and other things). To support defio, affected drivers require
682 be awesome if those tests (at least the ones not relying on Intel-specific GEM
Ddrm-vm-bind-async.rst183 * @obj: GEM object to operate on, MBZ for MAP_USERPTR, MBZ for UNMAP
223 /* Unmap a gem object from the VM. */
Ddrm-kms-helpers.rst83 GEM Atomic Helper Reference
143 Framebuffer GEM Helper Reference
/Documentation/devicetree/bindings/net/
Dcdns,macb.yaml7 title: Cadence MACB/GEM Ethernet controller
23 - cdns,zynq-gem # Xilinx Zynq-7xxx SoC
24 - cdns,zynqmp-gem # Xilinx Zynq Ultrascale+ MPSoC
25 - const: cdns,gem # Generic
30 - xlnx,versal-gem # Xilinx Versal
31 - xlnx,zynq-gem # Xilinx Zynq-7xxx SoC
32 - xlnx,zynqmp-gem # Xilinx Zynq Ultrascale+ MPSoC
33 - const: cdns,gem # Generic
50 - atmel,sama5d29-gem # GEM XL IP (10/100) on Atmel sama5d29 SoCs
51 - atmel,sama5d2-gem # GEM IP (10/100) on Atmel sama5d2 SoCs
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/Documentation/devicetree/bindings/interconnect/
Dqcom,rpmh.yaml33 - qcom,sc7180-gem-noc
45 - qcom,sc8180x-gem-noc
78 - qcom,sm8150-gem-noc
87 - qcom,sm8250-gem-noc
97 - qcom,sm8350-gem-noc
Dqcom,sc7280-rpmh.yaml28 - qcom,sc7280-gem-noc
112 compatible = "qcom,sc7280-gem-noc";
Dqcom,sc8280xp-rpmh.yaml27 - qcom,sc8280xp-gem-noc
Dqcom,sa8775p-rpmh.yaml26 - qcom,sa8775p-gem-noc
Dqcom,qdu1000-rpmh.yaml25 - qcom,qdu1000-gem-noc
Dqcom,sm6350-rpmh.yaml25 - qcom,sm6350-gem-noc
Dqcom,sdx75-rpmh.yaml25 - qcom,sdx75-gem-noc
Dqcom,sm7150-rpmh.yaml29 - qcom,sm7150-gem-noc
Dqcom,x1e80100-rpmh.yaml31 - qcom,x1e80100-gem-noc
Dqcom,sm8450-rpmh.yaml26 - qcom,sm8450-gem-noc
Dqcom,sm8550-rpmh.yaml31 - qcom,sm8550-gem-noc
Dqcom,sm8650-rpmh.yaml31 - qcom,sm8650-gem-noc
/Documentation/devicetree/bindings/clock/
Dxlnx,versal-clk.yaml108 - description: GEM emio clock (Optional clock)
120 - pattern: "gem[0-3]+_emio_clk.*$"
/Documentation/gpu/rfc/
Di915_vm_bind.rst7 DRM_I915_GEM_VM_BIND/UNBIND ioctls allows UMD to bind/unbind GEM buffer
31 * Support for userptr gem objects (no special uapi is required for this).
63 default gem context and many more (See struct drm_i915_gem_execbuffer3).
128 find the backing storage (dma_resv lock for gem objects, and hmm/core mm for
238 VM_BIND interface can be used to map system memory directly (without gem BO

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