Searched full:generation (Results 1 – 25 of 199) sorted by relevance
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| /Documentation/devicetree/bindings/iommu/ |
| D | mediatek,iommu.yaml | 14 this M4U have two generations of HW architecture. Generation one uses flat
15 pagetable, and only supports 4K size page mapping. Generation two uses the
73 - mediatek,mt2701-m4u # generation one
74 - mediatek,mt2712-m4u # generation two
75 - mediatek,mt6779-m4u # generation two
76 - mediatek,mt6795-m4u # generation two
77 - mediatek,mt8167-m4u # generation two
78 - mediatek,mt8173-m4u # generation two
79 - mediatek,mt8183-m4u # generation two
80 - mediatek,mt8186-iommu-mm # generation two
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| /Documentation/driver-api/surface_aggregator/ |
| D | overview.rst | 9 introduced on 4th generation devices (Surface Pro 4, Surface Book 1), but
17 Not much is currently known about SAM on 4th generation devices (Surface Pro
20 Book 2, Surface Laptop 1) and later generation devices, SAM is responsible
28 restructured for 7th generation devices and on those, specifically Surface
33 generation, internal interfaces have undergone some rather large changes. On
34 5th and 6th generation devices, both battery and temperature information is
37 requests. On 7th generation devices, this additional layer is gone and these
49 generation of the Surface device. On 4th generation devices, host and EC
67 communication interface for SAM on 5th- and all later-generation Surface
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| /Documentation/devicetree/bindings/memory-controllers/ |
| D | mediatek,smi-common.yaml | 17 which generation the SoCs use:
18 generation 1: mt2701 and mt7623.
19 generation 2: mt2712, mt6779, mt8167, mt8173, mt8183, mt8186, mt8188, mt8192 and mt8195.
21 There's slight differences between the two SMI, for generation 2, the
23 for generation 1, the register is at smi ao base(smi always on register
25 SMI generation 1 to transform the smi clock into emi clock domain, but that is
26 not needed for SMI generation 2.
61 apb and smi are mandatory. the async is only for generation 1 smi HW.
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| /Documentation/devicetree/bindings/clock/ |
| D | imx7ulp-scg-clock.yaml | 7 title: Freescale i.MX7ULP System Clock Generation (SCG) modules Clock Controller
14 Clock Generation (SCG) modules, Peripheral Clock Control (PCC)
28 The System Clock Generation (SCG) is responsible for clock generation
30 include: clock reference selection, generation of clock used to derive
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| D | imx8ulp-cgc-clock.yaml | 7 title: NXP i.MX8ULP Clock Generation & Control(CGC) Module
13 On i.MX8ULP, The clock sources generation, distribution and management is
37 # Clock Generation & Control Module node:
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| D | sophgo,sg2042-pll.yaml | 21 - description: Oscillator(Clock Generation IC) for Main/Fixed PLL (25 MHz)
22 - description: Oscillator(Clock Generation IC) for DDR PLL 0 (25 MHz)
23 - description: Oscillator(Clock Generation IC) for DDR PLL 1 (25 MHz)
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| D | renesas,rzv2h-cpg.yaml | 13 On Renesas RZ/V2H(P) SoCs, the CPG (Clock Pulse Generator) handles generation
14 and control of clock signals for the IP modules, generation and control of resets,
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| /Documentation/mm/ |
| D | multigen_lru.rst | 23 implementations. In the multi-gen LRU, each generation represents a
45 attainable. Specifically, pages in the same generation can be
83 ``lruvec``. The youngest generation number is stored in
85 an equal footing. The oldest generation numbers are stored in
90 Generation numbers are truncated into ``order_base_2(MAX_NR_GENS+1)``
92 truncated generation number is an index to ``lrugen->folios[]``. The
98 Each generation is divided into multiple tiers. A page accessed ``N``
117 generation when it finds them accessed through page tables; the
139 moves a page to the next generation, i.e., ``min_seq+1``, if this page
147 Each generation is timestamped at birth. If ``lru_gen_min_ttl`` is
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| /Documentation/devicetree/bindings/rng/ |
| D | microsoft,vmgenid.yaml | 7 title: Virtual Machine Generation ID
14 interrupt and a shared resource to inject a Virtual Machine Generation ID.
15 Virtual Machine Generation ID is a globally unique identifier (GUID) and
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| /Documentation/filesystems/ext4/ |
| D | checksums.rst | 50 - UUID + inode number + inode generation + the directory block up to the
54 - UUID + inode number + inode generation + all valid extents + HTREE tail.
58 - UUID + inode number + inode generation + the entire extent block up to
66 - UUID + inode number + inode generation + the entire inode. The checksum
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| /Documentation/devicetree/bindings/nvmem/ |
| D | brcm,ocotp.txt | 4 - compatible: "brcm,ocotp" for the first generation Broadcom OTPC which is used
6 generation Broadcom OTPC which is used in SoC's such as Stingray and supports
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| /Documentation/virt/kvm/x86/ |
| D | mmu.rst | 62 The mmu supports first-generation mmu hardware, which allows an atomic switch
212 The MMU generation of this page, used to fast zap of all MMU pages within a
214 valid MMU generation which causes the mismatch of mmu_valid_gen for each mmu
217 guest. The MMU generation is only ever '0' or '1'. Note, the TDP MMU doesn't
341 - check for valid generation number in the spte (see "Fast invalidation of
475 generation number. The global generation number is stored in
476 kvm_memslots(kvm)->generation, and increased whenever guest memory info
479 When KVM finds an MMIO spte, it checks the generation number of the spte.
480 If the generation number of the spte does not equal the global generation
484 Since only 18 bits are used to store generation-number on mmio spte, all
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| /Documentation/admin-guide/media/ |
| D | technisat.rst | 37 (except ``Simple tuner support`` for ATSC 3rd generation only -> see case 9 please).
87 - AirStar ATSC card 1st generation:
91 - AirStar ATSC card 2nd generation:
96 - AirStar ATSC card 3rd generation:
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| /Documentation/sound/cards/ |
| D | pcmtest.rst | 40 Capture Data Generation
43 The driver has two modes of data generation: the first (0 in the fill_mode parameter)
44 means random data generation, the second (1 in the fill_mode) - pattern-based
45 data generation. Let's look at the second mode.
47 First of all, you may want to specify the pattern for data generation. You can do it
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| /Documentation/devicetree/bindings/soc/renesas/ |
| D | renesas,rzv2m-pwc.yaml | 12 - external power supply on/off sequence generation
13 - on/off signal generation for the LPDDR4 core power supply (LPVDD)
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| /Documentation/devicetree/bindings/pci/ |
| D | brcm,iproc-pcie.yaml | 20 # for the first generation of PAXB based controller, used in SoCs
23 # for the second generation of PAXB-based controllers, used in
26 # For the first generation of PAXC based controller, used in NS2
28 # For the second generation of PAXC based controller, used in Stingray
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| /Documentation/userspace-api/media/dvb/ |
| D | fe-set-tone.rst | 13 FE_SET_TONE - Sets/resets the generation of the continuous 22kHz tone.
34 This ioctl is used to set the generation of the continuous 22kHz tone.
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| /Documentation/networking/device_drivers/ethernet/google/ |
| D | gve.rst | 153 "generation bit" to know when a descriptor was populated by the device. The
154 driver initializes all bits with the "current generation". The device will
155 populate received descriptors with the "next generation" which is inverted
156 from the current generation. When the ring wraps, the current/next generation
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| /Documentation/devicetree/bindings/gpio/ |
| D | ti,omap-gpio.yaml | 15 and output capabilities; interrupt generation in active mode and wake-up
16 request generation in idle mode upon the detection of external events.
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| /Documentation/networking/dsa/ |
| D | sja1105.rst | 10 - SJA1105E: First generation, no TTEthernet
11 - SJA1105T: First generation, TTEthernet
12 - SJA1105P: Second generation, no TTEthernet, no SGMII
13 - SJA1105Q: Second generation, TTEthernet, no SGMII
14 - SJA1105R: Second generation, no TTEthernet, SGMII
15 - SJA1105S: Second generation, TTEthernet, SGMII
16 - SJA1110A: Third generation, TTEthernet, SGMII, integrated 100base-T1 and
18 - SJA1110B: Third generation, TTEthernet, SGMII, 100base-T1, 100base-TX
19 - SJA1110C: Third generation, TTEthernet, SGMII, 100base-T1, 100base-TX
20 - SJA1110D: Third generation, TTEthernet, SGMII, 100base-T1
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| /Documentation/misc-devices/ |
| D | dw-xdata-pcie.rst | 33 Write TLPs traffic generation - Root Complex to Endpoint direction
49 Read TLPs traffic generation - Endpoint to Root Complex direction
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| /Documentation/ABI/testing/ |
| D | sysfs-class-mei | 28 are decoded depends on PCH or SoC generation.
30 depending on generation.
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| /Documentation/devicetree/bindings/phy/ |
| D | phy-miphy365x.txt | 33 - st,sata-gen : Generation of locally attached SATA IP. Expected values
34 are {1,2,3). If not supplied generation 1 hardware will
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| /Documentation/arch/arm/sti/ |
| D | stih407-overview.rst | 8 The STiH407 is the new generation of SoC for Multi-HD, AVC set-top boxes
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| /Documentation/devicetree/bindings/mips/lantiq/ |
| D | lantiq,cgu.yaml | 7 title: Lantiq Xway SoC series Clock Generation Unit (CGU)
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