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/Documentation/devicetree/bindings/mfd/
Dbrcm,bcm63268-gpio-sysctl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mfd/brcm,bcm63268-gpio-sysctl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Broadcom BCM63268 GPIO System Controller
10 - Álvaro Fernández Rojas <noltari@gmail.com>
11 - Jonas Gorski <jonas.gorski@gmail.com>
14 Broadcom BCM63268 SoC GPIO system controller which provides a register map
15 for controlling the GPIO and pins of the SoC.
18 "#address-cells": true
[all …]
Dbrcm,bcm6362-gpio-sysctl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mfd/brcm,bcm6362-gpio-sysctl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Broadcom BCM6362 GPIO System Controller
10 - Álvaro Fernández Rojas <noltari@gmail.com>
11 - Jonas Gorski <jonas.gorski@gmail.com>
14 Broadcom BCM6362 SoC GPIO system controller which provides a register map
15 for controlling the GPIO and pins of the SoC.
18 "#address-cells": true
[all …]
Dbrcm,bcm6318-gpio-sysctl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mfd/brcm,bcm6318-gpio-sysctl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Broadcom BCM6318 GPIO System Controller
10 - Álvaro Fernández Rojas <noltari@gmail.com>
11 - Jonas Gorski <jonas.gorski@gmail.com>
14 Broadcom BCM6318 SoC GPIO system controller which provides a register map
15 for controlling the GPIO and pins of the SoC.
18 "#address-cells": true
[all …]
Dbrcm,bcm6368-gpio-sysctl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mfd/brcm,bcm6368-gpio-sysctl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Broadcom BCM6368 GPIO System Controller
10 - Álvaro Fernández Rojas <noltari@gmail.com>
11 - Jonas Gorski <jonas.gorski@gmail.com>
14 Broadcom BCM6368 SoC GPIO system controller which provides a register map
15 for controlling the GPIO and pins of the SoC.
18 "#address-cells": true
[all …]
Dbrcm,bcm6328-gpio-sysctl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mfd/brcm,bcm6328-gpio-sysctl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Broadcom BCM6328 GPIO System Controller
10 - Álvaro Fernández Rojas <noltari@gmail.com>
11 - Jonas Gorski <jonas.gorski@gmail.com>
14 Broadcom BCM6328 SoC GPIO system controller which provides a register map
15 for controlling the GPIO and pins of the SoC.
18 "#address-cells": true
[all …]
Dbrcm,bcm6358-gpio-sysctl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mfd/brcm,bcm6358-gpio-sysctl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Broadcom BCM6358 GPIO System Controller
10 - Álvaro Fernández Rojas <noltari@gmail.com>
11 - Jonas Gorski <jonas.gorski@gmail.com>
14 Broadcom BCM6358 SoC GPIO system controller which provides a register map
15 for controlling the GPIO and pins of the SoC.
18 "#address-cells": true
[all …]
/Documentation/devicetree/bindings/pinctrl/
Dmarvell,armada-37xx-pinctrl.txt1 * Marvell Armada 37xx SoC pin and gpio controller
3 Each Armada 37xx SoC come with two pin and gpio controller one for the
6 Inside this set of register the gpio latch allows exposing some
11 GPIO and pin controller:
12 ------------------------
16 Refer to pinctrl-bindings.txt in this directory for details of the
22 - compatible: "marvell,armada3710-sb-pinctrl", "syscon, "simple-mfd"
24 "marvell,armada3710-nb-pinctrl", "syscon, "simple-mfd"
26 - reg: The first set of register are for pinctrl/gpio and the second
28 - interrupts: list of the interrupt use by the gpio
[all …]
Dsunplus,sp7021-pinctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/pinctrl/sunplus,sp7021-pinctrl.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Dvorkin Dmitry <dvorkin@tibbo.com>
12 - Wells Lu <wellslutw@gmail.com>
15 The Sunplus SP7021 pin controller is used to control SoC pins. Please
16 refer to pinctrl-bindings.txt in this directory for details of the common
19 SP7021 has 99 digital GPIO pins which are numbered from GPIO 0 to 98. All
20 are multiplexed with some special function pins. SP7021 has 3 types of
[all …]
Dmarvell,dove-pinctrl.txt3 Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding
7 - compatible: "marvell,dove-pinctrl"
8 - clocks: (optional) phandle of pdma clock
9 - reg: register specifiers of MPP, MPP4, and PMU MPP registers
11 Available mpp pins/groups and functions:
16 name pins functions
18 mpp0 0 gpio, pmu, uart2(rts), sdio0(cd), lcd0(pwm), pmu*
19 mpp1 1 gpio, pmu, uart2(cts), sdio0(wp), lcd1(pwm), pmu*
20 mpp2 2 gpio, pmu, uart2(txd), sdio0(buspwr), sata(prsnt),
22 mpp3 3 gpio, pmu, uart2(rxd), sdio0(ledctrl), sata(act),
[all …]
Dawinic,aw9523-pinctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/awinic,aw9523-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Awinic AW9523/AW9523B I2C GPIO Expander
10 - AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
13 The Awinic AW9523/AW9523B I2C GPIO Expander featuring 16 multi-function
18 const: awinic,aw9523-pinctrl
23 '#gpio-cells':
26 include/dt-bindings/gpio/gpio.h
[all …]
Dsamsung,pinctrl.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Krzysztof Kozlowski <krzk@kernel.org>
11 - Sylwester Nawrocki <s.nawrocki@samsung.com>
12 - Tomasz Figa <tomasz.figa@gmail.com>
22 - External GPIO interrupts (see interrupts property in pin controller node);
24 - External wake-up interrupts - multiplexed (capable of waking up the system
25 see interrupts property in external wake-up interrupt controller node -
26 samsung,pinctrl-wakeup-interrupt.yaml);
[all …]
Dcypress,cy8c95x0.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Cypress CY8C95X0 I2C GPIO expander
10 - Patrick Rudolph <patrick.rudolph@9elements.com>
13 This supports the 20/40/60 pin Cypress CYC95x0 GPIO I2C expanders.
14 Pin function configuration is performed on a per-pin basis.
19 - cypress,cy8c9520
20 - cypress,cy8c9540
21 - cypress,cy8c9560
[all …]
Dmediatek,mt8195-pinctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/mediatek,mt8195-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Sean Wang <sean.wang@mediatek.com>
13 The MediaTek's MT8195 Pin controller is used to control SoC pins.
17 const: mediatek,mt8195-pinctrl
19 gpio-controller: true
21 '#gpio-cells':
23 Number of cells in GPIO specifier. Since the generic GPIO binding is used,
[all …]
Dqcom,sm4450-tlmm.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/qcom,sm4450-tlmm.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Tengfei Fan <quic_tengfan@quicinc.com>
16 - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
20 const: qcom,sm4450-tlmm
26 interrupt-controller: true
27 "#interrupt-cells": true
28 gpio-controller: true
[all …]
Dste,abx500.txt4 - compatible: "stericsson,ab8500-gpio", "stericsson,ab8540-gpio",
5 "stericsson,ab8505-gpio", "stericsson,ab9540-gpio",
7 Please refer to pinctrl-bindings.txt in this directory for details of the
12 and pin configuration bindings, see pinctrl-bindings.txt
17 pinctrl-names = "default";
18 …pinctrl-0 = <&sysclkreq2_default_mode>, <&sysclkreq3_default_mode>, <&gpio3_default_mode>, <&syscl…
27 pins = "GPIO1";
28 bias-disable;
39 pins = "GPIO2";
40 output-low;
[all …]
Dmediatek,mt8186-pinctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/mediatek,mt8186-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Sean Wang <sean.wang@mediatek.com>
13 The MediaTek's MT8186 Pin controller is used to control SoC pins.
17 const: mediatek,mt8186-pinctrl
19 gpio-controller: true
21 '#gpio-cells':
23 Number of cells in GPIO specifier. Since the generic GPIO binding is used,
[all …]
Dmscc,ocelot-pinctrl.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/mscc,ocelot-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Alexandre Belloni <alexandre.belloni@bootlin.com>
11 - Lars Povlsen <lars.povlsen@microchip.com>
16 - microchip,lan966x-pinctrl
17 - microchip,sparx5-pinctrl
18 - mscc,jaguar2-pinctrl
19 - mscc,luton-pinctrl
[all …]
Dsemtech,sx1501q.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Semtech SX150x GPIO expander
11 - Neil Armstrong <neil.armstrong@linaro.org>
16 - semtech,sx1501q
17 - semtech,sx1502q
18 - semtech,sx1503q
19 - semtech,sx1504q
20 - semtech,sx1505q
[all …]
Dqcom,msm8974-pinctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/qcom,msm8974-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Bjorn Andersson <andersson@kernel.org>
11 - Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
18 const: qcom,msm8974-pinctrl
26 gpio-reserved-ranges:
30 gpio-line-names:
34 "-state$":
[all …]
Dmediatek,mt6795-pinctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/mediatek,mt6795-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
11 - Sean Wang <sean.wang@kernel.org>
14 The MediaTek's MT6795 Pin controller is used to control SoC pins.
18 const: mediatek,mt6795-pinctrl
20 gpio-controller: true
22 '#gpio-cells':
[all …]
Dqcom,msm8960-pinctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/qcom,msm8960-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Bjorn Andersson <andersson@kernel.org>
11 - Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
18 const: qcom,msm8960-pinctrl
26 gpio-reserved-ranges:
30 gpio-line-names:
34 "-state$":
[all …]
Dqcom,sm6115-tlmm.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/qcom,sm6115-tlmm.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Iskren Chernev <iskren.chernev@gmail.com>
18 const: qcom,sm6115-tlmm
23 reg-names:
25 - const: west
26 - const: south
27 - const: east
[all …]
Dingenic,pinctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 Please refer to pinctrl-bindings.txt in this directory for details of the
14 For the Ingenic SoCs, pin control is tightly bound with GPIO ports. All pins
16 GPIO port configuration registers and it is typical to refer to pins using the
17 naming scheme "PxN" where x is a character identifying the GPIO port with
19 pin within that GPIO port. For example PA0 is the first pin in GPIO port A,
20 and PB31 is the last pin in GPIO port B. The JZ4730, the JZ4740, the JZ4725B,
21 the X1000 and the X1830 contains 4 GPIO ports, PA to PD, for a total of 128
[all …]
Dpinctrl-rk805.txt3 RK805 has 2 pins which can be configured as GPIO output only.
5 Please refer file <devicetree/bindings/pinctrl/pinctrl-bindings.txt>
10 --------------------------
11 Following properties are required if default setting of pins are required
13 - pinctrl-names: A pinctrl state named per <pinctrl-bindings.txt>.
14 - pinctrl[0...n]: Properties to contain the phandle for pinctrl states per
15 <pinctrl-bindings.txt>.
18 sub-node have following properties:
21 ------------------
22 - #gpio-cells: Should be two. The first cell is the pin number and the
[all …]
/Documentation/driver-api/
Dpin-control.rst9 - Enumerating and naming controllable pins
11 - Multiplexing of pins, pads, fingers (etc) see below for details
13 - Configuration of pins, pads, fingers (etc), such as software-controlled
14 biasing and driving mode specific pins, such as pull-up, pull-down, open drain,
17 Top-level interface
22 - A PIN CONTROLLER is a piece of hardware, usually a set of registers, that
23 can control PINs. It may be able to multiplex, bias, set load capacitance,
24 set drive strength, etc. for individual pins or groups of pins.
26 - PINS are equal to pads, fingers, balls or whatever packaging input or
30 be sparse - i.e. there may be gaps in the space with numbers where no
[all …]

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