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/Documentation/devicetree/bindings/clock/
Dqcom,mmcc.yaml113 - description: MMSS GPLL0 voted clock
114 - description: GPLL0 voted clock
141 - description: MMSS GPLL0 voted clock
142 - description: GPLL0 voted clock
180 - description: MMSS GPLL0 voted clock
181 - description: GPLL0 clock
182 - description: GPLL0 voted clock
197 - const: gpll0
244 - const: gpll0
274 - const: gpll0
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Dqcom,msm8998-gpucc.yaml25 - description: GPLL0 main branch source (gcc_gpu_gpll0_clk_src)
30 - const: gpll0
54 clock-names = "xo", "gpll0";
Dqcom,sm6115-gpucc.yaml26 - description: GPLL0 main branch source
27 - description: GPLL0 main div source
Dqcom,gpucc-sdm660.yaml27 - description: GPLL0 main gpu branch
28 - description: GPLL0 divider gpu branch
Dqcom,qcm2290-gpucc.yaml30 - description: GPLL0 main branch source
31 - description: GPLL0 div branch source
Dqcom,sm6375-gpucc.yaml26 - description: GPLL0 main branch source
27 - description: GPLL0 div branch source
Dqcom,qcm2290-dispcc.yaml26 - description: GPLL0 source from GCC
27 - description: GPLL0 div source from GCC
Dqcom,sm8450-gpucc.yaml36 - description: GPLL0 main branch source
37 - description: GPLL0 div branch source
Dqcom,sdm845-dispcc.yaml28 - description: GPLL0 source from GCC
29 - description: GPLL0 div source from GCC
Dqcom,gpucc.yaml44 - description: GPLL0 main branch source
45 - description: GPLL0 div branch source
Dqcom,sm6115-dispcc.yaml29 - description: GPLL0 DISP DIV clock from GCC
Dqcom,sm6125-gpucc.yaml26 - description: GPLL0 main branch source
Dqcom,sm6375-dispcc.yaml28 - description: GPLL0 source from GCC
Dqcom,dispcc-sm6350.yaml25 - description: GPLL0 source from GCC
Dqcom,sc7180-dispcc.yaml25 - description: GPLL0 source from GCC
Dqcom,qdu1000-ecpricc.yaml30 - description: GPLL0 source from GCC
Dqcom,sc7280-dispcc.yaml25 - description: GPLL0 source from GCC
Dqcom,sm7150-dispcc.yaml28 - description: GPLL0 source from GCC
Dqcom,dispcc-sm6125.yaml32 - description: GPLL0 div source from GCC
/Documentation/devicetree/bindings/interconnect/
Dqcom,osm-l3.yaml66 #define GPLL0 165
73 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
/Documentation/devicetree/bindings/mailbox/
Dqcom,apcs-kpss-global.yaml158 - description: GCC GPLL0 clock source
163 - const: gpll0
/Documentation/devicetree/bindings/remoteproc/
Dqcom,msm8996-mss-pil.yaml220 - description: GCC MSS GPLL0 clock
255 - description: GCC MSS GPLL0 clock
292 - description: GCC MSS GPLL0 clock
/Documentation/devicetree/bindings/cpufreq/
Dcpufreq-qcom-hw.yaml69 - description: GPLL0 Clock
364 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;