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/Documentation/gpu/amdgpu/
Ddebugging.rst2 GPU Debugging
8 To aid in debugging GPU virtual memory related problems, the driver supports a
11 `vm_fault_stop` - If non-0, halt the GPU memory controller on a GPU page fault.
13 `vm_update_mode` - If non-0, use the CPU to update GPU page tables rather than
14 the GPU.
20 If you see a GPU page fault in the kernel log, you can decode it to figure
26 …[gfxhub0] no-retry page fault (src_id:0 ring:24 vmid:3 pasid:32777, for process glxinfo pid 2424 t…
29 Faulty UTCL2 client ID: TCP (0x8)
38 memory hub used for multi-media and sdma on some chips.
41 caused by the kernel driver or firmware. If the vmid is non-0, it is generally
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/Documentation/devicetree/bindings/gpu/
Dimg,powervr-sgx.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 # Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/
5 ---
6 $id: http://devicetree.org/schemas/gpu/img,powervr-sgx.yaml#
7 $schema: http://devicetree.org/meta-schemas/core.yaml#
12 - Frank Binns <frank.binns@imgtec.com>
17 - items:
18 - enum:
19 - ti,omap3430-gpu # Rev 121
20 - ti,omap3630-gpu # Rev 125
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Dvivante,gc.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/gpu/vivante,gc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Vivante GPU
9 description: Vivante GPU core devices
12 - Lucas Stach <l.stach@pengutronix.de>
24 '#cooling-cells':
27 assigned-clock-parents: true
28 assigned-clock-rates: true
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Dimg,powervr-rogue.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/gpu/img,powervr-rogue.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Frank Binns <frank.binns@imgtec.com>
16 - enum:
17 - ti,am62-gpu
18 - const: img,img-axe # IMG AXE GPU model/revision is fully discoverable
27 clock-names:
29 - const: core
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Darm,mali-valhall-csf.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/gpu/arm,mali-valhall-csf.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ARM Mali Valhall GPU
10 - Liviu Dudau <liviu.dudau@arm.com>
11 - Boris Brezillon <boris.brezillon@collabora.com>
15 pattern: '^gpu@[a-f0-9]+$'
19 - items:
20 - enum:
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Dbrcm,bcm-v3d.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/gpu/brcm,bcm-v3d.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Broadcom V3D GPU
10 - Eric Anholt <eric@anholt.net>
11 - Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
15 pattern: '^gpu@[a-f0-9]+$'
19 - brcm,2711-v3d
20 - brcm,2712-v3d
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Darm,mali-bifrost.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/gpu/arm,mali-bifrost.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ARM Mali Bifrost GPU
10 - Rob Herring <robh@kernel.org>
14 pattern: '^gpu@[a-f0-9]+$'
18 - items:
19 - enum:
20 - amlogic,meson-g12a-mali
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Darm,mali-midgard.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/gpu/arm,mali-midgard.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ARM Mali Midgard GPU
10 - Rob Herring <robh@kernel.org>
14 pattern: '^gpu@[a-f0-9]+$'
17 - items:
18 - enum:
19 - samsung,exynos5250-mali
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Darm,mali-utgard.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/gpu/arm,mali-utgard.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ARM Mali Utgard GPU
10 - Rob Herring <robh@kernel.org>
11 - Maxime Ripard <mripard@kernel.org>
12 - Heiko Stuebner <heiko@sntech.de>
16 pattern: '^gpu@[a-f0-9]+$'
19 - items:
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/Documentation/devicetree/bindings/display/msm/
Dgpu.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $id: http://devicetree.org/schemas/display/msm/gpu.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Rob Clark <robdclark@gmail.com>
14 # as a work-around:
20 - qcom,adreno
21 - amd,imageon
23 - compatible
28 - description: |
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Dgmu.yaml1 # SPDX-License-Identifier: GPL-2.0-only
2 # Copyright 2019-2020, The Linux Foundation, All Rights Reserved
4 ---
6 $id: http://devicetree.org/schemas/display/msm/gmu.yaml#
7 $schema: http://devicetree.org/meta-schemas/core.yaml#
12 - Rob Clark <robdclark@gmail.com>
16 to members of the Adreno A6xx GPU family. The GMU provides on-device power
23 - items:
24 - pattern: '^qcom,adreno-gmu-[67][0-9][0-9]\.[0-9]$'
25 - const: qcom,adreno-gmu
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/Documentation/gpu/
Dmsm-crash-dump.rst7 Following a GPU hang the MSM driver outputs debugging information via
14 by a (-).
17 --------
35 ID of the GPU that generated the crash formatted as
38 rbbm-status
39 The current value of RBBM_STATUS which shows what top level GPU
44 identified with an id number.
46 id
47 Ringbuffer ID (0 based index). Each ringbuffer in the section
48 will have its own unique id.
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Di915.rst17 ------------------------
19 .. kernel-doc:: drivers/gpu/drm/i915/intel_runtime_pm.c
22 .. kernel-doc:: drivers/gpu/drm/i915/intel_runtime_pm.c
25 .. kernel-doc:: drivers/gpu/drm/i915/intel_uncore.c
29 ------------------
31 .. kernel-doc:: drivers/gpu/drm/i915/i915_irq.c
34 .. kernel-doc:: drivers/gpu/drm/i915/i915_irq.c
37 .. kernel-doc:: drivers/gpu/drm/i915/i915_irq.c
40 .. kernel-doc:: drivers/gpu/drm/i915/i915_irq.c
43 Intel GVT-g Guest Support(vGPU)
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Ddrm-uapi.rst9 addition, drivers export device-specific interfaces for use by userspace
10 drivers & device-aware applications through ioctls and sysfs files.
16 Cover generic ioctls and sysfs layout here. We only need high-level
22 .. kernel-doc:: drivers/gpu/drm/drm_ioctl.c
31 .. kernel-doc:: drivers/gpu/drm/drm_auth.c
34 .. kernel-doc:: drivers/gpu/drm/drm_auth.c
37 .. kernel-doc:: include/drm/drm_auth.h
46 .. kernel-doc:: drivers/gpu/drm/drm_lease.c
49 Open-Source Userspace Requirements
57 open-sourced userspace patches, and those patches must be reviewed and ready for
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Ddrm-vm-bind-async.rst1 .. SPDX-License-Identifier: (GPL-2.0+ OR MIT)
10 * ``VRAM``: On-device memory. Sometimes referred to as device local memory.
12 * ``gpu_vm``: A virtual GPU address space. Typically per process, but
16 an IOCTL. The operations include mapping and unmapping system- or
20 synchronization objects can be either generic, like dma-fences or
24 * ``in-syncobj``: Argument to a VM_BIND IOCTL, the VM_BIND operation waits
27 * ``out-syncobj``: Argument to a VM_BIND_IOCTL, the VM_BIND operation
30 * ``dma-fence``: A cross-driver synchronization object. A basic
31 understanding of dma-fences is required to digest this
33 :doc:`dma-buf doc </driver-api/dma-buf>`.
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/Documentation/admin-guide/perf/
Dnvidia-pmu.rst9 * NVLink-C2C0
10 * NVLink-C2C1
15 ----------
19 PMUs are managed by a common driver "arm-cs-arch-pmu". This driver describes
22 the driver provides "cpumask" sysfs attribute to show the CPU id used to handle
29 -------
32 strongly-ordered (SO) PCIE write traffic to local/remote memory. Please see
37 see /sys/bus/event_sources/devices/nvidia_scf_pmu_<socket-id>.
41 * Count event id 0x0 in socket 0::
43 perf stat -a -e nvidia_scf_pmu_0/event=0x0/
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/Documentation/driver-api/
Dedac.rst5 ----------------------------------------
8 *sockets, *socket sets*, *banks*, *rows*, *chip-select rows*, *channels*,
43 It is typically the highest hierarchy on a Fully-Buffered DIMM memory
52 * Single-channel
55 only. E. g. if the data is 64 bits-wide, the data flows to the CPU using
57 memories. FB-DIMM and RAMBUS use a different concept for channel, so
60 * Double-channel
63 dimms, accessed at the same time. E. g. if the DIMM is 64 bits-wide (72
67 * Chip-select row
70 accessed. Common chip-select rows for single channel are 64 bits, for
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/Documentation/devicetree/bindings/iommu/
Darm,smmu.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/iommu/arm,smmu.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Will Deacon <will@kernel.org>
11 - Robin Murphy <Robin.Murphy@arm.com>
23 pattern: "^iommu@[0-9a-f]*"
26 - description: Qcom SoCs implementing "arm,smmu-v2"
28 - enum:
29 - qcom,msm8996-smmu-v2
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/Documentation/devicetree/bindings/display/
Dbrcm,bcm2835-vc4.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/display/brcm,bcm2835-vc4.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Broadcom VC4 (VideoCore4) GPU
10 - Eric Anholt <eric@anholt.net>
20 - brcm,bcm2711-vc5
21 - brcm,bcm2835-vc4
22 - brcm,cygnus-vc4
25 - compatible
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/Documentation/gpu/rfc/
Di915_vm_bind.h1 /* SPDX-License-Identifier: MIT */
32 * Flag to opt-in for VM_BIND mode of binding during VM creation.
51 * struct drm_i915_gem_timeline_fence - An input or output timeline fence.
74 #define __I915_TIMELINE_FENCE_UNKNOWN_FLAGS (-(I915_TIMELINE_FENCE_SIGNAL << 1))
86 * struct drm_i915_gem_vm_bind - VA to object mapping to bind.
88 * This structure is passed to VM_BIND ioctl and specifies the mapping of GPU
98 * platform, for binding device local-memory objects, the @start, @offset and
102 * Error code -EINVAL will be returned if @start, @offset and @length are not
104 * -ENOSPC will be returned if the VA range specified can't be reserved.
111 /** @vm_id: VM (address space) id to bind */
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/Documentation/devicetree/bindings/thermal/
Dnvidia,tegra124-soctherm.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/thermal/nvidia,tegra124-soctherm.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
14 polled or interrupt-based thermal monitoring, CPU and GPU throttling based
21 - nvidia,tegra124-soctherm
22 - nvidia,tegra132-soctherm
23 - nvidia,tegra210-soctherm
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/Documentation/devicetree/bindings/timer/
Dbrcm,bcm2835-system-timer.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/timer/brcm,bcm2835-system-timer.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Stefan Wahren <wahrenst@gmx.net>
11 - Raspberry Pi Kernel Maintenance <kernel-list@raspberrypi.com>
14 The System Timer peripheral provides four 32-bit timer channels and a
15 single 64-bit free running counter. Each channel has an output compare
21 const: brcm,bcm2835-system-timer
28 - description: System Timer Compare 0 match (used by VideoCore GPU)
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/Documentation/devicetree/bindings/clock/
Dqcom,gpucc-sdm660.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,gpucc-sdm660.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
16 See also dt-bindings/clock/qcom,gpucc-sdm660.h.
21 - qcom,gpucc-sdm630
22 - qcom,gpucc-sdm660
26 - description: Board XO source
27 - description: GPLL0 main gpu branch
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Dsprd,sc9860-clk.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/clock/sprd,sc9860-clk.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Orson Zhai <orsonzhai@gmail.com>
11 - Baolin Wang <baolin.wang7@gmail.com>
12 - Chunyan Zhang <zhang.lyra@gmail.com>
17 - sprd,sc9860-agcp-gate
18 - sprd,sc9860-aonsecure-clk
19 - sprd,sc9860-aon-gate
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/Documentation/devicetree/bindings/usb/
Dcypress,cypd4226.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/usb/cypress,cypd4226.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Cypress cypd4226 Type-C Controller
10 - Wayne Chang <waynec@nvidia.com>
13 The Cypress cypd4226 is a dual Type-C controller that is controlled
20 '#address-cells':
23 '#size-cells':
31 - description: cypd4226 host interrupt
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