Searched +full:hart +full:- +full:index +full:- +full:bits (Results 1 – 2 of 2) sorted by relevance
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)3 ---4 $id: http://devicetree.org/schemas/interrupt-controller/riscv,imsics.yaml#5 $schema: http://devicetree.org/meta-schemas/core.yaml#7 title: RISC-V Incoming MSI Controller (IMSIC)10 - Anup Patel <anup@brainfault.org>13 The RISC-V advanced interrupt architecture (AIA) defines a per-CPU incoming14 MSI controller (IMSIC) for handling MSIs in a RISC-V platform. The RISC-V15 AIA specification can be found at https://github.com/riscv/riscv-aia.17 The IMSIC is a per-CPU (or per-HART) device with separate interrupt file[all …]
1 .. SPDX-License-Identifier: GPL-2.08 ----------------------12 ./scripts/config -e PCI13 ./scripts/config -m I2C14 ./scripts/config -m INPUT15 ./scripts/config -m MEDIA_SUPPORT16 ./scripts/config -e MEDIA_PCI_SUPPORT17 ./scripts/config -e MEDIA_ANALOG_TV_SUPPORT18 ./scripts/config -e MEDIA_DIGITAL_TV_SUPPORT19 ./scripts/config -e MEDIA_RADIO_SUPPORT[all …]