Searched +full:has +full:- +full:chip +full:- +full:id (Results 1 – 25 of 185) sorted by relevance
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| /Documentation/devicetree/bindings/mips/ |
| D | mscc.txt | 7 - compatible: "mscc,ocelot", "mscc,luton", "mscc,serval" or "mscc,jr2"
12 o CPU chip regs:
14 The SoC has a few registers (DEVCPU_GCB:CHIP_REGS) handling miscellaneous
15 functionalities: chip ID, general purpose register for software use, reset
19 - compatible: Should be "mscc,ocelot-chip-regs", "simple-mfd", "syscon"
20 - reg : Should contain registers location and length
24 compatible = "mscc,ocelot-chip-regs", "simple-mfd", "syscon";
30 The SoC has a few registers (HSIO) handling miscellaneous functionalities:
35 - compatible: Should be "mscc,ocelot-hsio", "syscon", "simple-mfd"
36 - reg : Should contain registers location and length
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| /Documentation/devicetree/bindings/arm/ |
| D | arm,vexpress-juno.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/arm/arm,vexpress-juno.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Sudeep Holla <sudeep.holla@arm.com>
11 - Linus Walleij <linus.walleij@linaro.org>
15 multicore Cortex-A class systems. The Versatile Express family contains both
37 further subvariants are released of the core tile, even more fine-granular
45 - description: CoreTile Express A9x4 (V2P-CA9) has 4 Cortex A9 CPU cores
46 in MPCore configuration in a test chip on the core tile. See ARM
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| /Documentation/devicetree/bindings/devfreq/event/ |
| D | samsung,exynos-nocp.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/devfreq/event/samsung,exynos-nocp.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Samsung Exynos NoC (Network on Chip) Probe
10 - Chanwoo Choi <cw00.choi@samsung.com>
11 - Krzysztof Kozlowski <krzk@kernel.org>
14 The Samsung Exynos542x SoC has a NoC (Network on Chip) Probe for NoC bus.
16 that the Network on Chip (NoC) probes detects are transported over the
19 traffic debug or statistic collectors. Exynos542x bus has multiple NoC probes
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| /Documentation/hwmon/ |
| D | sis5595.rst | 10 Addresses scanned: ISA in PCI-space encoded address
18 - Kyösti Mälkki <kmalkki@cc.hut.fi>,
19 - Mark D. Studebaker <mdsxyz123@yahoo.com>,
20 - Aurelien Jarno <aurelien@aurel32.net> 2.6 port
22 SiS southbridge has a LM78-like chip integrated on the same IC.
28 Version PCI ID PCI Revision
36 "blacklist" PCI ID and refuse to load.
39 NOT SUPPORTED PCI ID BLACKLIST PCI ID
55 -----------------
69 -----------
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| D | w83791d.rst | 10 Addresses scanned: I2C 0x2c - 0x2f
12 Datasheet: http://www.winbond-usa.com/products/winbond_products/pdfs/PCIC/W83791D_W83791Gb.pdf
22 - Frodo Looijaard <frodol@dds.nl>,
23 - Philip Edelbrock <phil@netroedge.com>,
24 - Mark Studebaker <mdsxyz123@yahoo.com>
28 - Shane Huang (Winbond),
29 - Rudolf Marek <r.marek@assembler.cz>
33 - Sven Anders <anders@anduras.de>
34 - Marc Hulsman <m.hulsman@tudelft.nl>
37 -----------------
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| /Documentation/driver-api/ |
| D | edac.rst | 5 ----------------------------------------
8 *sockets, *socket sets*, *banks*, *rows*, *chip-select rows*, *channels*,
38 DIMMs. Each channel has its own independent control (command) and data
43 It is typically the highest hierarchy on a Fully-Buffered DIMM memory
52 * Single-channel
55 only. E. g. if the data is 64 bits-wide, the data flows to the CPU using
57 memories. FB-DIMM and RAMBUS use a different concept for channel, so
60 * Double-channel
63 dimms, accessed at the same time. E. g. if the DIMM is 64 bits-wide (72
67 * Chip-select row
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| D | pwm.rst | 15 ----------------
19 Instead of referring to a PWM device via its unique ID, board setup code
24 PWM_LOOKUP("tegra-pwm", 0, "pwm-backlight", NULL,
36 ----------
42 After being requested, a PWM has to be configured using::
64 maintain the power output but has more freedom regarding signal form.
66 EMI by phase shifting the individual channels of a chip.
76 different to what the driver has actually implemented if the request cannot be
82 PWM arguments are usually platform-specific and allows the PWM user to only
93 -----------------------------------
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| D | mtdnand.rst | 10 The generic NAND driver supports almost all NAND and AG-AND based chips
26 struct member has a short description which is marked with an [XXX]
31 --------------------------
37 - [MTD Interface]
43 - [NAND Interface]
48 - [GENERIC]
53 - [DEFAULT]
58 via pointers in the NAND chip description structure. The board driver
62 function which is suitable for the detected chip type.
65 -------------------------------
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| /Documentation/devicetree/bindings/arm/amlogic/ |
| D | amlogic,meson-gx-ao-secure.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/arm/amlogic/amlogic,meson-gx-ao-secure.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Neil Armstrong <neil.armstrong@linaro.org>
22 const: amlogic,meson-gx-ao-secure
24 - compatible
29 - items:
30 - const: amlogic,meson-gx-ao-secure
31 - const: syscon
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| /Documentation/devicetree/bindings/timestamp/ |
| D | nvidia,tegra194-hte.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/timestamp/nvidia,tegra194-hte.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Tegra on chip generic hardware timestamping engine (HTE) provider
10 - Dipen Patel <dipenp@nvidia.com>
13 Tegra SoC has two instances of generic hardware timestamping engines (GTE)
14 known as GTE GPIO and GTE IRQ, which can monitor subset of GPIO and on chip
16 timestamp (taken from system counter) in its internal hardware FIFO. It has
24 - nvidia,tegra194-gte-aon
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| /Documentation/ABI/testing/ |
| D | sysfs-driver-jz4780-efuse | 1 What: /sys/devices/*/<our-device>/nvmem
4 Description: read-only access to the efuse on the Ingenic JZ4780 SoC
5 The SoC has a one time programmable 8K efuse that is
11 0x008 128 bit Ingenic Chip ID
12 0x018 128 bit Customer ID
19 Users: any user space application which wants to read the Chip
20 and Customer ID
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| D | sysfs-devices-platform-kunpeng_hccs | 9 contains read-only attributes exposing some summarization
10 information of all HCCS ports under a specified chip.
11 The X in 'chipX' indicates the Xth chip on platform.
16 all_linked: (RO) if all enabled ports on this chip are
18 linked_full_lane: (RO) if all linked ports on this chip are full
21 chip.
32 contains read-only attributes exposing some summarization
34 The Y in 'dieY' indicates the hardware id of the die on chip who
35 has chip id X.
60 contains read-only attributes exposing information about
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| D | sysfs-devices-soc | 5 The /sys/devices/ directory contains a sub-directory for each
6 System-on-Chip (SoC) device on a running platform. Information
12 It has been agreed that if an SoC device exists, its supported
19 Read-only attribute common to all SoCs. Contains the SoC machine
26 Read-only attribute common to all SoCs. Contains SoC family name
39 scheme has been defined.
47 For example, ARM has identity code 0x7F 0x7F 0x7F 0x7F 0x3B,
57 Read-only attribute supported by most SoCs. Contains the SoC's
64 Read-only attribute supported by most SoCs. In the case of
65 ST-Ericsson's chips this contains the SoC serial number.
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| /Documentation/devicetree/bindings/spi/ |
| D | sprd,spi-adi.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/spi/sprd,spi-adi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Orson Zhai <orsonzhai@gmail.com>
11 - Baolin Wang <baolin.wang7@gmail.com>
12 - Chunyan Zhang <zhang.lyra@gmail.com>
15 ADI is the abbreviation of Anolog-Digital interface, which is used to access
16 analog chip (such as PMIC) from digital chip. ADI controller follows the SPI
20 ADI controller has 50 channels including 2 software read/write channels and
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| /Documentation/devicetree/bindings/pwm/ |
| D | pwm-sifive.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/pwm/pwm-sifive.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Paul Walmsley <paul.walmsley@sifive.com>
16 run at the same period. The period also has significant restrictions on
19 numbers can be found here -
21 https://github.com/sifive/sifive-blocks/tree/master/src/main/scala/devices/pwm
24 - $ref: pwm.yaml#
29 - enum:
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| /Documentation/devicetree/bindings/mailbox/ |
| D | mediatek,gce-props.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mailbox/mediatek,gce-props.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Houlong Wei <houlong.wei@mediatek.com>
13 The Global Command Engine (GCE) is an instruction based, multi-threaded,
14 single-core command dispatcher for MediaTek hardware. The Command Queue
18 We use mediatek,gce-mailbox.yaml to define the properties for CMDQ mailbox
28 mediatek,gce-events:
30 GCE has an event table in SRAM, consisting of 1024 event IDs (0~1023).
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| /Documentation/devicetree/bindings/i2c/ |
| D | i2c-gpio.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/i2c/i2c-gpio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Wolfram Sang <wsa@kernel.org>
13 - $ref: /schemas/i2c/i2c-controller.yaml#
18 - const: i2c-gpio
20 sda-gpios:
24 from <dt-bindings/gpio/gpio.h> since the signal is by definition
28 scl-gpios:
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| /Documentation/admin-guide/gpio/ |
| D | gpio-mockup.rst | 1 .. SPDX-License-Identifier: GPL-2.0-only
8 This module has been obsoleted by the more flexible gpio-sim.rst.
14 The GPIO Testing Driver (gpio-mockup) provides a way to create simulated GPIO
20 --------------------------------------------
22 When loading the gpio-mockup driver a number of parameters can be passed to the
28 pairs. Each pair defines the base GPIO number (non-negative integer)
29 and the first number after the last of this chip. If the base GPIO
30 is -1, the gpiolib will assign it automatically. while the following
31 parameter is the number of lines exposed by the chip.
33 Example: gpio_mockup_ranges=-1,8,-1,16,405,409
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| /Documentation/devicetree/bindings/thermal/ |
| D | nvidia,tegra30-tsensor.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/thermal/nvidia,tegra30-tsensor.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Dmitry Osipenko <digetx@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
12 - Thierry Reding <thierry.reding@gmail.com>
16 and voltage of the chip. Sensors are placed across the die to gauge the
17 temperature of the whole chip. The TSENSOR module:
26 levels to reset the chip and sets a flag in the PMC.
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| /Documentation/devicetree/bindings/hwmon/ |
| D | ti,ina3221.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/hwmon/ti,ina3221.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jean Delvare <jdelvare@suse.com>
11 - Guenter Roeck <linux@roeck-us.net>
20 ti,single-shot:
22 This chip has two power modes: single-shot (chip takes one measurement
23 and then shuts itself down) and continuous (chip takes continuous
25 hardware monitor type device, but the single-shot mode is more power-
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| /Documentation/devicetree/bindings/net/bluetooth/ |
| D | mediatek,mt7921s-bluetooth.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/bluetooth/mediatek,mt7921s-bluetooth.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Sean Wang <sean.wang@mediatek.com>
13 MT7921S is an SDIO-attached dual-radio WiFi+Bluetooth Combo chip; each
14 function is its own SDIO function on a shared SDIO interface. The chip
15 has two dedicated reset lines, one for each function core.
20 - $ref: bluetooth-controller.yaml#
25 - mediatek,mt7921s-bluetooth
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| /Documentation/devicetree/bindings/dma/ |
| D | sifive,fu540-c000-pdma.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/dma/sifive,fu540-c000-pdma.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Green Wan <green.wan@sifive.com>
11 - Palmer Debbelt <palmer@sifive.com>
12 - Paul Walmsley <paul.walmsley@sifive.com>
16 channels. Each channel has 2 interrupts. One is for DMA done and
23 https://static.dev.sifive.com/FU540-C000-v1.0.pdf
26 - $ref: dma-controller.yaml#
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| /Documentation/userspace-api/media/v4l/ |
| D | ext-ctrls-flash.rst | 1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
3 .. _flash-controls:
17 .. _flash-controls-use-cases:
24 ------------------------------------------
35 ----------------------------------------
37 The synchronised LED flash is pre-programmed by the host (power and
46 ------------------
52 .. _flash-control-id:
55 -----------------
61 Defines the mode of the flash LED, the high-power white LED attached
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| /Documentation/devicetree/bindings/bus/ |
| D | qcom,ebi2.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/bus/qcom,ebi2.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 external memory (such as NAND or other memory-mapped peripherals) whereas
17 NOR flash memories), WE (write enable). This on top of 6 different chip selects
20 Apparently this bus is clocked at 64MHz. It has dedicated pins on the package
25 Also CS1 and CS2 has -A and -B signals. Why they have that is unclear to me.
27 The chip selects have the following memory range assignments. This region of
28 memory is referred to as "Chip Peripheral SS FPB0" and is 168MB big.
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| /Documentation/w1/masters/ |
| D | ds2490.rst | 13 -----------
15 The Maxim/Dallas Semiconductor DS2490 is a chip
16 which allows to build USB <-> W1 bridges.
18 DS9490(R) is a USB <-> W1 bus master device
19 which has 0x81 family ID integrated chip and DS2490
20 low-level operational chip.
24 - The weak pullup current is a minimum of 0.9mA and maximum of 6.0mA.
25 - The 5V strong pullup is supported with a minimum of 5.9mA and a
27 - The hardware will detect when devices are attached to the bus on the
31 - The number of USB bus transactions could be reduced if w1_reset_send
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