Searched +full:has +full:- +full:ecc (Results 1 – 25 of 27) sorted by relevance
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| /Documentation/driver-api/ |
| D | mtdnand.rst | 10 The generic NAND driver supports almost all NAND and AG-AND based chips
26 struct member has a short description which is marked with an [XXX]
31 --------------------------
37 - [MTD Interface]
43 - [NAND Interface]
48 - [GENERIC]
53 - [DEFAULT]
65 -------------------------------
71 - [INTERN]
77 - [REPLACEABLE]
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| D | edac.rst | 5 ----------------------------------------
8 *sockets, *socket sets*, *banks*, *rows*, *chip-select rows*, *channels*,
21 typically 72 bits, in order to provide 64 bits + 8 bits of ECC data.
38 DIMMs. Each channel has its own independent control (command) and data
43 It is typically the highest hierarchy on a Fully-Buffered DIMM memory
52 * Single-channel
55 only. E. g. if the data is 64 bits-wide, the data flows to the CPU using
57 memories. FB-DIMM and RAMBUS use a different concept for channel, so
60 * Double-channel
63 dimms, accessed at the same time. E. g. if the DIMM is 64 bits-wide (72
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| /Documentation/devicetree/bindings/memory-controllers/ |
| D | xlnx,zynq-ddrc-a05.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/xlnx,zynq-ddrc-a05.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Krzysztof Kozlowski <krzk@kernel.org>
11 - Michal Simek <michal.simek@amd.com>
14 The Zynq DDR ECC controller has an optional ECC support in half-bus width
15 (16-bit) configuration. It is capable of correcting single bit ECC errors
16 and detecting double bit ECC errors.
20 const: xlnx,zynq-ddrc-a05
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| D | snps,dw-umctl2-ddrc.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/snps,dw-umctl2-ddrc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Synopsys DesignWare Universal Multi-Protocol Memory Controller
10 - Krzysztof Kozlowski <krzk@kernel.org>
11 - Michal Simek <michal.simek@amd.com>
16 be equipped with SEC/DEC ECC feature if DRAM data bus width is either
17 16-bits or 32-bits or 64-bits wide.
20 controller. It has an optional SEC/DEC ECC support in 64- and 32-bits
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| D | xlnx,versal-ddrmc-edac.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/xlnx,versal-ddrmc-edac.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Shubhrajyoti Datta <shubhrajyoti.datta@amd.com>
11 - Sai Krishna Potthuri <sai.krishna.potthuri@amd.com>
15 4X memory interfaces. Versal DDR memory controller has an optional ECC support
16 which correct single bit ECC errors and detect double bit ECC errors.
20 const: xlnx,versal-ddrmc
24 - description: DDR Memory Controller registers
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| /Documentation/devicetree/bindings/mtd/ |
| D | brcm,brcmnand.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Brian Norris <computersforpeace@gmail.com>
11 - Kamal Dasu <kdasu.kdev@gmail.com>
12 - William Zhang <william.zhang@broadcom.com>
15 The Broadcom Set-Top Box NAND controller supports low-level access to raw NAND
16 flash chips. It has a memory-mapped register interface for both control
27 -- Additional SoC-specific NAND controller properties --
35 interesting ways, sometimes with registers that lump multiple NAND-related
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| D | vf610-nfc.txt | 7 - compatible: Should be set to "fsl,vf610-nfc".
8 - reg: address range of the NFC.
9 - interrupts: interrupt of the NFC.
10 - #address-cells: shall be set to 1. Encode the nand CS.
11 - #size-cells : shall be set to 0.
12 - assigned-clocks: main clock from the SoC, for Vybrid <&clks VF610_CLK_NFC>;
13 - assigned-clock-rates: The NAND bus timing is derived from this clock
17 there might be restrictions on maximum rates when using hardware ECC.
19 - #address-cells, #size-cells : Must be present if the device has sub-nodes
27 - compatible: Should be set to "fsl,vf610-nfc-cs".
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| D | raw-nand-chip.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mtd/raw-nand-chip.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Miquel Raynal <miquel.raynal@bootlin.com>
13 - $ref: nand-chip.yaml#
16 The ECC strength and ECC step size properties define the user
18 they request the ECC engine to correct {strength} bit errors per
21 The interpretation of these parameters is implementation-defined, so
28 pattern: "^nand@[a-f0-9]$"
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| D | atmel-nand.txt | 4 Documentation/devicetree/bindings/memory-controllers/atmel,ebi.txt).
6 The NAND controller might be connected to an ECC engine.
11 - compatible: should be one of the following
12 "atmel,at91rm9200-nand-controller"
13 "atmel,at91sam9260-nand-controller"
14 "atmel,at91sam9261-nand-controller"
15 "atmel,at91sam9g45-nand-controller"
16 "atmel,sama5d3-nand-controller"
17 "microchip,sam9x60-nand-controller"
18 - ranges: empty ranges property to forward EBI ranges definitions.
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| /Documentation/firmware-guide/acpi/apei/ |
| D | output_format.rst | 1 .. SPDX-License-Identifier: GPL-2.0
55 [cache error][, TLB error][, bus error][, micro-architectural error]
81 unknown | no error | single-bit ECC | multi-bit ECC | \
82 single-symbol chipkill ECC | multi-symbol chipkill ECC | master abort | \
106 downstream switch port | PCIe to PCI/PCI-X bridge | \
107 PCI/PCI-X to PCIe bridge | root complex integrated endpoint device | \
121 Replay Timer Timeout | Advisory Non-Fatal
132 All <field string> description with * has the following format::
139 All <field strings> description with # has the following format::
|
| /Documentation/devicetree/bindings/net/can/ |
| D | xilinx,can.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Appana Durga Kedareswara rao <appana.durga.rao@xilinx.com>
16 - xlnx,zynq-can-1.0
17 - xlnx,axi-can-1.00.a
18 - xlnx,canfd-1.0
19 - xlnx,canfd-2.0
31 clock-names:
34 power-domains:
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| /Documentation/devicetree/bindings/scsi/ |
| D | hisilicon-sas.txt | 6 - compatible : value should be as follows:
7 (a) "hisilicon,hip05-sas-v1" for v1 hw in hip05 chipset
8 (b) "hisilicon,hip06-sas-v2" for v2 hw in hip06 chipset
9 (c) "hisilicon,hip07-sas-v2" for v2 hw in hip07 chipset
10 - sas-addr : array of 8 bytes for host SAS address
11 - reg : Contains two regions. The first is the address and length of the SAS
15 - hisilicon,sas-syscon: phandle of syscon used for sas control
16 - ctrl-reset-reg : offset to controller reset register in ctrl reg
17 - ctrl-reset-sts-reg : offset to controller reset status register in ctrl reg
18 - ctrl-clock-ena-reg : offset to controller clock enable register in ctrl reg
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| /Documentation/devicetree/bindings/memory-controllers/ti/ |
| D | emif.txt | 3 EMIF - External Memory Interface - is an SDRAM controller used in
7 of the EMIF controller also contain optional ECC support, which
11 - compatible : Should be of the form "ti,emif-<ip-rev>" where <ip-rev>
14 "ti,emif-am3352"
15 "ti,emif-am4372"
16 "ti,emif-dra7xx"
17 "ti,emif-keystone"
19 - phy-type : <u32> indicating the DDR phy type. Following are the
24 - device-handle : phandle to a "lpddr2" node representing the memory part
26 - ti,hwmods : For TI hwmods processing and omap device creation
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| /Documentation/driver-api/mtd/ |
| D | nand_ecc.rst | 2 NAND Error-correction Code
8 Having looked at the linux mtd/nand Hamming software ECC engine driver
11 After that the speed was increased by 35-40%.
22 NAND flash (at least SLC one) typically has sectors of 256 bytes.
31 As I said before the ecc calculation is performed on sectors of 256
41 Back to ecc.
63 - cp0 is the parity that belongs to all bit0, bit2, bit4, bit6.
69 - cp2 is the parity over bit0, bit1, bit4 and bit5
70 - cp3 is the parity over bit2, bit3, bit6 and bit7.
71 - cp4 is the parity over bit0, bit1, bit2 and bit3.
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| /Documentation/admin-guide/RAS/ |
| D | main.rst | 1 .. SPDX-License-Identifier: GPL-2.0
37 -------------
48 * Memory – add error correction logic (ECC) to detect and correct errors;
51 Self-Monitoring, Analysis and Reporting Technology (SMART).
59 ---------------
72 * **Correctable Error (CE)** - the error detection mechanism detected and
76 * **Uncorrected Error (UE)** - the amount of errors happened above the error
77 correction threshold, and the system was unable to auto-correct.
79 * **Fatal Error** - when an UE error happens on a critical component of the
83 * **Non-fatal Error** - when an UE error happens on an unused component,
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| /Documentation/misc-devices/ |
| D | xilinx_sdfec.rst | 1 .. SPDX-License-Identifier: GPL-2.0+
4 Xilinx SD-FEC Driver
10 This driver supports SD-FEC Integrated Block for Zynq |Ultrascale+ (TM)| RFSoCs.
15 …f SD-FEC core features, see the `SD-FEC Product Guide (PG256) <https://www.xilinx.com/cgi-bin/docs…
19 - Retrieval of the Integrated Block configuration and status information
20 - Configuration of LDPC codes
21 - Configuration of Turbo decoding
22 - Monitoring errors
24 Missing features, known issues, and limitations of the SD-FEC driver are as
27 - Only allows a single open file handler to any instance of the driver at any time
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| /Documentation/devicetree/bindings/powerpc/fsl/ |
| D | pamu.txt | 5 The PAMU is an I/O MMU that provides device-to-memory access control and
10 - compatible : <string>
11 First entry is a version-specific string, such as
12 "fsl,pamu-v1.0". The second is "fsl,pamu".
13 - ranges : <prop-encoded-array>
18 PAMU v1.0, on an SOC that has five PAMU devices, the size
20 - interrupts : <prop-encoded-array>
24 and ECC errors.
25 - #address-cells: <u32>
27 - #size-cells : <u32>
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| /Documentation/mm/ |
| D | hwpoison.rst | 17 hardware as being corrupted usually due to a 2bit ECC memory or cache
24 just ignore it because no corruption has been consumed yet. Instead
31 has to be extremely careful. Generally it tries to use normal locking
41 The code consists of a the high level handler in mm/memory-failure.c,
46 of applications. KVM support requires a recent qemu-kvm release.
109 * madvise(MADV_HWPOISON, ....) (as root) - Poison a page in the
112 * hwpoison-inject module through debugfs ``/sys/kernel/debug/hwpoison/``
114 corrupt-pfn
118 unpoison-pfn
119 Software-unpoison page at PFN echoed into this file. This way
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| /Documentation/arch/arm/ |
| D | arm.rst | 9 ---------------------
21 If you wish to cross-compile, then alter the following lines in the top
36 CROSS_COMPILE=<your-path-to-your-compiler-without-gcc>
40 CROSS_COMPILE=arm-linux-
48 ---------------
54 Bug reports should be sent to linux-arm-kernel@lists.arm.linux.org.uk,
64 -------------
66 Several new include directories have been created under include/asm-arm,
67 which are there to reduce the clutter in the top-level directory. These
71 `arch-*` machine/platform specific header files
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| /Documentation/process/ |
| D | maintainer-pgp-guide.rst | 12 Linux Foundation. Please read that document for more in-depth discussion
15 .. _`Protecting Code Integrity`: https://github.com/lfit/itpol/blob/master/protecting-code-integrit…
22 communication channels between developers via PGP-signed email exchange.
26 - Distributed source repositories (git)
27 - Periodic release snapshots (tarballs)
35 - git repositories provide PGP signatures on all tags
36 - tarballs provide detached PGP signatures with all downloads
41 -------------------------------------------
44 operating principle of the Kernel Archives project has been to assume
64 ----------------------
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| /Documentation/networking/device_drivers/ethernet/stmicro/ |
| D | stmmac.rst | 1 .. SPDX-License-Identifier: GPL-2.0+
13 - In This Release
14 - Feature List
15 - Kernel Configuration
16 - Command Line Parameters
17 - Driver Information and Notes
18 - Debug Information
19 - Support
33 (and older) and DesignWare(R) Cores Ethernet Quality-of-Service version 4.0
35 DesignWare(R) Cores XGMAC - 10G Ethernet MAC and DesignWare(R) Cores
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| /Documentation/filesystems/ |
| D | proc.rst | 1 .. SPDX-License-Identifier: GPL-2.0
24 1.1 Process-Specific Subdirectories
36 3 Per-Process Parameters
37 3.1 /proc/<pid>/oom_adj & /proc/<pid>/oom_score_adj - Adjust the oom-killer
39 3.2 /proc/<pid>/oom_score - Display current oom-killer score
40 3.3 /proc/<pid>/io - Display the IO accounting fields
41 3.4 /proc/<pid>/coredump_filter - Core dump filtering settings
42 3.5 /proc/<pid>/mountinfo - Information about mounts
44 3.7 /proc/<pid>/task/<tid>/children - Information about task children
45 3.8 /proc/<pid>/fdinfo/<fd> - Information about opened file
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| /Documentation/admin-guide/sysctl/ |
| D | kernel.rst | 5 .. See scripts/check-sysctl-docs to keep this up to date
13 Documentation/admin-guide/sysctl/index.rst.
15 ------------------------------------------------------------------------------
39 If BSD-style process accounting is enabled these values control
71 The machine hardware name, the same output as ``uname -m``
77 This variable has no effect and may be removed in future kernel
129 Ctrl-Alt-Delete). Writing a value to this file which doesn't
130 correspond to a running process will result in ``-ESRCH``.
132 See also `ctrl-alt-del`_.
236 ctrl-alt-del
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| /Documentation/RCU/Design/Requirements/ |
| D | Requirements.rst | 16 ------------
18 Read-copy update (RCU) is a synchronization mechanism that is often used
19 as a replacement for reader-writer locking. RCU is unusual in that
20 updaters do not block readers, which means that RCU's read-side
28 thought of as an informal, high-level specification for RCU. It is
32 has this learning process been a lot of fun, but it has also been a
40 #. `Fundamental Non-Requirements`_
42 #. `Quality-of-Implementation Requirements`_
44 #. `Software-Engineering Requirements`_
53 ------------------------
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| /Documentation/arch/s390/ |
| D | vfio-ap.rst | 13 The AP adapter cards are exposed via the AP bus. The motivation for vfio-ap
45 sub-directory::
76 significant bit, correspond to domains 0-255.
111 * NQAP: to enqueue an AP command-request message to a queue
112 * DQAP: to dequeue an AP command-reply message from a queue
127 Block (APCB) that has three fields to identify the adapters, usage domains and
132 an APID from 0-255. If a bit is set, the corresponding adapter is valid for
137 corresponds to an AP queue index (APQI) from 0-255. If a bit is set, the
142 changed by an AP command-request message sent to a usage domain from the
144 0-255. If a bit is set, the corresponding domain can be modified by an AP
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