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| /Documentation/userspace-api/media/v4l/ |
| D | pixfmt-z16.rst | 1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
3 .. _V4L2-PIX-FMT-Z16:
10 16-bit depth data with distance values at each pixel
16 This is a 16-bit format, representing depth data. Each pixel is a
17 distance to the respective point in the image coordinates. Distance unit
18 can vary and has to be negotiated with the device separately. Each pixel
19 is stored in a 16-bit word in the little endian byte order.
27 .. flat-table::
28 :header-rows: 0
29 :stub-columns: 0
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| D | pixfmt-tch-tu16.rst | 1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
3 .. _V4L2-TCH-FMT-TU16:
11 16-bit unsigned little endian raw touch data
17 This format represents unsigned 16-bit data from a touch controller.
20 0 to 65535.
26 .. flat-table::
27 :header-rows: 0
28 :stub-columns: 0
31 * - start + 0:
32 - R'\ :sub:`00low`
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| D | pixfmt-tch-td16.rst | 1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
3 .. _V4L2-TCH-FMT-DELTA-TD16:
11 16-bit signed little endian Touch Delta
19 Delta values may range from -32768 to 32767. Typically the values will vary
27 .. flat-table::
28 :header-rows: 0
29 :stub-columns: 0
32 * - start + 0:
33 - D'\ :sub:`00low`
34 - D'\ :sub:`00high`
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| D | pixfmt-srggb10-ipu3.rst | 1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
3 .. _v4l2-pix-fmt-ipu3-sbggr10:
4 .. _v4l2-pix-fmt-ipu3-sgbrg10:
5 .. _v4l2-pix-fmt-ipu3-sgrbg10:
6 .. _v4l2-pix-fmt-ipu3-srggb10:
13 10-bit Bayer formats
21 to 32 bytes leaving 6 most significant bits padding in the last byte.
24 In other respects this format is similar to :ref:`V4L2-PIX-FMT-SRGGB10`.
36 .. flat-table::
38 * - start + 0:
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| D | pixfmt-srggb12.rst | 1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
3 .. _V4L2-PIX-FMT-SRGGB12:
4 .. _v4l2-pix-fmt-sbggr12:
5 .. _v4l2-pix-fmt-sgbrg12:
6 .. _v4l2-pix-fmt-sgrbg12:
17 12-bit Bayer formats expanded to 16 bits
24 colour. Each colour component is stored in a 16-bit word, with 4 unused
25 high bits filled with zeros. Each n-pixel row contains n/2 green samples
32 Each cell is one byte, the 4 most significant bits in the high bytes are
38 .. flat-table::
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| D | pixfmt-srggb10.rst | 1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
3 .. _V4L2-PIX-FMT-SRGGB10:
4 .. _v4l2-pix-fmt-sbggr10:
5 .. _v4l2-pix-fmt-sgbrg10:
6 .. _v4l2-pix-fmt-sgrbg10:
16 10-bit Bayer formats expanded to 16 bits
23 sample. Each sample is stored in a 16-bit word, with 6 unused
24 high bits filled with zeros. Each n-pixel row contains n/2 green samples and
31 Each cell is one byte, the 6 most significant bits in the high bytes
37 .. flat-table::
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| D | pixfmt-srggb14.rst | 1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
3 .. _V4L2-PIX-FMT-SRGGB14:
4 .. _v4l2-pix-fmt-sbggr14:
5 .. _v4l2-pix-fmt-sgbrg14:
6 .. _v4l2-pix-fmt-sgrbg14:
15 14-bit Bayer formats expanded to 16 bits
23 colour. Each sample is stored in a 16-bit word, with two unused high
24 bits filled with zeros. Each n-pixel row contains n/2 green samples
31 Each cell is one byte, the two most significant bits in the high bytes are
36 .. flat-table::
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| /Documentation/arch/arm64/ |
| D | kdump.rst | 7 Kdump mechanism is used to capture a corrupted kernel vmcore so that
8 it can be subsequently analyzed. In order to do this, a preliminarily
9 reserved memory is needed to pre-load the kdump kernel and boot such
12 That reserved memory for kdump is adapted to be able to minimally
21 large chunk of memomy can be found. The low memory reservation needs to
22 be considered if the crashkernel is reserved from the high memory area.
24 - crashkernel=size@offset
25 - crashkernel=size
26 - crashkernel=size,high crashkernel=size,low
28 Low memory and high memory
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| /Documentation/driver-api/gpio/ |
| D | intro.rst | 9 The documents in this directory give detailed instructions on how to access
10 GPIOs in drivers, and how to write a driver for a device that provides GPIOs
17 A "General Purpose Input/Output" (GPIO) is a flexible software-controlled
19 to Linux developers working with embedded and custom hardware. Each GPIO
20 represents a bit connected to a particular pin, or "ball" on Ball Grid Array
21 (BGA) packages. Board schematics show which external hardware connects to
23 passes such pin configuration data to drivers.
25 System-on-Chip (SOC) processors heavily rely on GPIOs. In some cases, every
26 non-dedicated pin can be configured as a GPIO; and most chips have at least
29 often have a few such pins to help with pin scarcity on SOCs; and there are
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| /Documentation/hwmon/ |
| D | adm9240.rst | 10 Addresses scanned: I2C 0x2c - 0x2f
20 Addresses scanned: I2C 0x2c - 0x2f
24 http://pdfserv.maxim-ic.com/en/ds/DS1780.pdf
30 Addresses scanned: I2C 0x2c - 0x2f
37 - Frodo Looijaard <frodol@dds.nl>,
38 - Philip Edelbrock <phil@netroedge.com>,
39 - Michiel Rook <michiel@grendelproject.nl>,
40 - Grant Coady <gcoady.lk@gmail.com> with guidance
44 ---------
46 chip MSB 5-bit address. Each chip reports a unique manufacturer
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| D | ltc2947.rst | 1 Kernel drivers ltc2947-i2c and ltc2947-spi
10 Addresses scanned: -
14 https://www.analog.com/media/en/technical-documentation/data-sheets/LTC2947.pdf
21 The LTC2947 is a high precision power and energy monitor that measures current,
25 register's to read/set energy related values. These banks can be configured
26 independently to have setups like: energy1 accumulates always and enrgy2 only
27 accumulates if current is positive (to check battery charging efficiency for
29 to control a fan as a function of measured temperature. Then, the GPIO becomes
31 temp2 channel is used to control this thresholds and to read the respective
37 The following attributes are supported. Limits are read-write, reset_history
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| D | ina2xx.rst | 10 Addresses: I2C 0x40 - 0x4f
20 Addresses: I2C 0x40 - 0x4f
30 Addresses: I2C 0x40 - 0x4f
40 Addresses: I2C 0x40 - 0x4f
50 Addresses: I2C 0x40 - 0x4f
59 -----------
61 The INA219 is a high-side current shunt and power monitor with an I2C
65 The INA220 is a high or low side current shunt and power monitor with an I2C
71 INA230 and INA231 are high or low side current shunt and power monitors
75 The shunt value in micro-ohms can be set via platform data or device tree at
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| D | max20751.rst | 10 Addresses scanned: -
16 Author: Guenter Roeck <linux@roeck-us.net>
20 -----------
25 The driver is a client driver to the core PMBus driver.
30 -----------
32 This driver does not auto-detect devices. You will have to instantiate the
33 devices explicitly. Please see Documentation/i2c/instantiating-devices.rst for
38 ---------------------
44 -------------
55 in1_min_alarm Input voltage low alarm.
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| D | max16065.rst | 11 Addresses scanned: -
15 http://datasheets.maxim-ic.com/en/ds/MAX16065-MAX16066.pdf
21 Addresses scanned: -
25 http://datasheets.maxim-ic.com/en/ds/MAX16067.pdf
31 Addresses scanned: -
35 http://datasheets.maxim-ic.com/en/ds/MAX16068.pdf
41 Addresses scanned: -
45 http://datasheets.maxim-ic.com/en/ds/MAX16070-MAX16071.pdf
47 Author: Guenter Roeck <linux@roeck-us.net>
51 -----------
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| D | spd5118.rst | 1 .. SPDX-License-Identifier: GPL-2.0-or-later
11 https://www.jedec.org/standards-documents/docs/jesd300-5b01
17 Addresses scanned: I2C 0x50 - 0x57
20 Guenter Roeck <linux@roeck-us.net>
24 -----------
28 to prevent memory overheating by automatically throttling the memory controller.
30 The driver auto-detects SPD5118 compliant chips, but can also be instantiated
35 for low critical, low, high, and critical thresholds.
39 ---------------------------------
43 temp1_lcrit Low critical high temperature (RW)
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| /Documentation/ABI/testing/ |
| D | sysfs-bus-iio-adc-hi8435 | 7 Could be either "GND-Open" or "Supply-Open" mode. Y is a
16 Channel Y low voltage threshold. If sensor input voltage goes lower then
18 Depending on in_voltageY_sensing_mode the low voltage threshold
19 is separately set for "GND-Open" and "Supply-Open" modes.
20 Channels 0..31 have common low threshold values, but could have different
23 The low voltage threshold range is between 2..21V.
24 Hysteresis between low and high thresholds can not be lower then 2 and
27 If falling threshold results hysteresis to odd value then rising
35 Channel Y high voltage threshold. If sensor input voltage goes higher then
37 Depending on in_voltageY_sensing_mode the high voltage threshold
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| D | sysfs-bus-pci-drivers-ehci_hcd | 7 PCI-based EHCI USB controllers (i.e., high-speed USB-2.0
9 "companion" full/low-speed USB-1.1 controllers. When a
10 high-speed device is plugged in, the connection is routed
11 to the EHCI controller; when a full- or low-speed device
12 is plugged in, the connection is routed to the companion
15 Sometimes you want to force a high-speed device to connect
17 connection to be routed to the companion controller.
18 That's what this file does. Writing a port number to the
19 file causes connections on that port to be routed to the
21 number returns the port to normal operation.
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| /Documentation/userspace-api/media/cec/ |
| D | cec-ioc-dqevent.rst | 1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
13 CEC_DQEVENT - Dequeue a CEC event
35 non-blocking mode and no event is pending, then it will return -1 and
36 set errno to the ``EAGAIN`` error code.
38 The internal event queues are per-filehandle and per-event type. If
42 possible to read two successive events that have the same value (e.g.
43 two :ref:`CEC_EVENT_STATE_CHANGE <CEC-EVENT-STATE-CHANGE>` events with
51 .. flat-table:: struct cec_event_state_change
52 :header-rows: 0
53 :stub-columns: 0
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| /Documentation/devicetree/bindings/iio/adc/ |
| D | adi,ad4000.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Analog Devices AD4000 and similar Analog to Digital Converters
10 - Marcelo Schmitt <marcelo.schmitt@analog.com>
13 Analog Devices AD4000 family of Analog to Digital Converters with SPI support.
15 https://www.analog.com/media/en/technical-documentation/data-sheets/ad4000-4004-4008.pdf
16 https://www.analog.com/media/en/technical-documentation/data-sheets/ad4001-4005.pdf
17 https://www.analog.com/media/en/technical-documentation/data-sheets/ad4002-4006-4010.pdf
18 https://www.analog.com/media/en/technical-documentation/data-sheets/ad4003-4007-4011.pdf
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| /Documentation/timers/ |
| D | hrtimers.rst | 2 hrtimers - subsystem for high-resolution kernel timers
5 This patch introduces a new subsystem for high-resolution kernel timers.
9 back and forth trying to integrate high-resolution and high-precision
11 such high-resolution timer implementations in practice, we came to the
14 to solve this'), and spent a considerable effort trying to integrate
18 - the forced handling of low-resolution and high-resolution timers in
19 the same way leads to a lot of compromises, macro magic and #ifdef
21 32-bitness assumptions, and has been honed and micro-optimized for a
23 for many years - and thus even small extensions to it easily break
24 the wheel concept, leading to even worse compromises. The timer wheel
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| /Documentation/devicetree/bindings/pinctrl/ |
| D | pincfg-node.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/pincfg-node.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Linus Walleij <linus.walleij@linaro.org>
21 bias-disable:
25 bias-high-impedance:
27 description: high impedance mode ("third-state", "floating")
29 bias-bus-hold:
33 bias-pull-up:
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| /Documentation/devicetree/bindings/sound/ |
| D | ti,tlv320adcx140.yaml | 1 # SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Texas Instruments TLV320ADCX140 Quad Channel Analog-to-Digital Converter
11 - Andrew Davis <afd@ti.com>
14 The TLV320ADCX140 are multichannel (4-ch analog recording or 8-ch digital
15 PDM microphones recording), high-performance audio, analog-to-digital
16 converter (ADC) with analog inputs supporting up to 2V RMS. The TLV320ADCX140
28 - ti,tlv320adc3140
29 - ti,tlv320adc5140
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| /Documentation/devicetree/bindings/reset/ |
| D | snps,dw-reset.txt | 4 Please also refer to reset.txt in this directory for common reset
9 - compatible: should be one of the following.
10 "snps,dw-high-reset" - for active high configuration
11 "snps,dw-low-reset" - for active low configuration
13 - reg: physical base address of the controller and length of memory mapped
16 - #reset-cells: must be 1.
20 dw_rst_1: reset-controller@0000 {
21 compatible = "snps,dw-high-reset";
23 #reset-cells = <1>;
26 dw_rst_2: reset-controller@1000 {
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| /Documentation/devicetree/bindings/serial/ |
| D | rs485.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 direction for the built-in half-duplex mode. The properties described
11 hereafter shall be given to a half-duplex capable UART node.
14 - Rob Herring <robh@kernel.org>
17 rs485-rts-delay:
18 description: prop-encoded-array <a b>
19 $ref: /schemas/types.yaml#/definitions/uint32-array
21 - description: Delay between rts signal and beginning of data sent in
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| /Documentation/devicetree/bindings/interrupt-controller/ |
| D | snps,archs-idu-intc.txt | 1 * ARC-HS Interrupt Distribution Unit
9 - compatible: "snps,archs-idu-intc"
10 - interrupt-controller: This is an interrupt controller.
11 - #interrupt-cells: Must be <1> or <2>.
13 Value of the first cell specifies the "common" IRQ from peripheral to IDU.
14 Number N of the particular interrupt line of IDU corresponds to the line N+24
18 - bits[3:0] trigger type and level flags
19 1 = low-to-high edge triggered
20 2 = NOT SUPPORTED (high-to-low edge triggered)
21 4 = active high level-sensitive <<< DEFAULT
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