Searched +full:hix5hd2 +full:- +full:clock (Results 1 – 4 of 4) sorted by relevance
| /Documentation/devicetree/bindings/i2c/ |
| D | i2c-hix5hd2.txt | 1 I2C for Hisilicon hix5hd2 chipset platform
4 - compatible: Must be "hisilicon,hix5hd2-i2c"
5 - reg: physical base address of the controller and length of memory mapped
7 - interrupts: interrupt number to the cpu.
8 - #address-cells = <1>;
9 - #size-cells = <0>;
10 - clocks: phandles to input clocks.
13 - clock-frequency: Desired I2C bus frequency in Hz, otherwise defaults to 100000
14 - Child nodes conforming to i2c bus binding
18 compatible = "hisilicon,hix5hd2-i2c";
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| /Documentation/devicetree/bindings/arm/hisilicon/controller/ |
| D | cpuctrl.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Wei Xu <xuwei5@hisilicon.com>
13 The clock registers and power registers of secondary cores are defined
14 in CPU controller, especially in HIX5HD2 SoC.
19 - const: hisilicon,cpuctrl
24 "#address-cells":
27 "#size-cells":
33 "^clock@[0-9a-f]+$":
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| /Documentation/devicetree/bindings/media/ |
| D | hix5hd2-ir.txt | 1 Device-Tree bindings for hix5hd2 ir IP
4 - compatible: Should contain "hisilicon,hix5hd2-ir", or:
5 - "hisilicon,hi3796cv300-ir" for Hi3796CV300 IR device.
6 - reg: Base physical address of the controller and length of memory
8 - interrupts: interrupt-specifier for the sole interrupt generated by
11 - clocks: clock phandle and specifier pair.
14 - linux,rc-map-name: see rc.txt file in the same directory.
15 - hisilicon,power-syscon: DEPRECATED. Don't use this in new dts files.
21 compatible = "hisilicon,hix5hd2-ir";
24 clocks = <&clock HIX5HD2_IR_CLOCK>;
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| /Documentation/devicetree/bindings/net/ |
| D | hisilicon-hix5hd2-gmac.txt | 1 Hisilicon hix5hd2 gmac controller
4 - compatible: should contain one of the following SoC strings:
5 * "hisilicon,hix5hd2-gmac"
6 * "hisilicon,hi3798cv200-gmac"
7 * "hisilicon,hi3516a-gmac"
9 * "hisilicon,hisi-gmac-v1"
10 * "hisilicon,hisi-gmac-v2"
11 The version v1 includes SoCs hix5hd2.
13 - reg: specifies base physical address(s) and size of the device registers.
16 - interrupts: should contain the MAC interrupt.
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