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/Documentation/devicetree/bindings/phy/
Dqcom,usb-hsic-phy.yaml4 $id: http://devicetree.org/schemas/phy/qcom,usb-hsic-phy.yaml#
7 title: Qualcomm USB HSIC PHY Controller
17 - qcom,usb-hsic-phy-mdm9615
18 - qcom,usb-hsic-phy-msm8974
19 - const: qcom,usb-hsic-phy
57 compatible = "qcom,usb-hsic-phy-msm8974",
58 "qcom,usb-hsic-phy";
Dmarvell,mmp3-hsic-phy.yaml5 $id: http://devicetree.org/schemas/phy/marvell,mmp3-hsic-phy.yaml#
8 title: Marvell MMP3 HSIC PHY
15 const: marvell,mmp3-hsic-phy
33 hsic-phy@f0001800 {
34 compatible = "marvell,mmp3-hsic-phy";
Dallwinner,sun9i-a80-usb-phy.yaml30 - description: HSIC 12MHz clock
31 - description: HSIC 480MHz clock
46 - description: HSIC Reset
52 - const: hsic
55 const: hsic
77 const: hsic
128 "hsic";
129 phy_type = "hsic";
Dnvidia,tegra186-xusb-padctl.yaml23 or high-speed USB (such as UTMI, ULPI and HSIC). The XUSB pad controller
80 vddio-hsic-supply:
81 description: HSIC PHY power supply. Must supply 1.2 V.
148 hsic:
154 - description: HSIC tracking clock
164 hsic-0:
346 hsic-0:
423 - vddio-hsic-supply
445 vddio-hsic-supply = <&gnd>;
470 hsic {
[all …]
Dmarvell,pxa1928-usb-phy.yaml7 title: Marvell PXA1928 USB/HSIC PHY
16 - marvell,pxa1928-hsic-phy
Dnvidia,tegra124-xusb-padctl.yaml23 or high-speed USB (such as UTMI, ULPI and HSIC). The XUSB pad controller
165 hsic:
171 - description: HSIC tracking clock
181 hsic-0:
193 hsic-1:
448 hsic-0:
456 hsic-1:
564 hsic {
566 hsic-0 {
571 hsic-1 {
[all …]
Dnvidia,tegra210-xusb-padctl.yaml23 or high-speed USB (such as UTMI, ULPI and HSIC). The XUSB pad controller
155 hsic:
161 - description: HSIC tracking clock
171 hsic-0:
183 hsic-1:
503 hsic-0:
511 hsic-1:
657 hsic {
663 hsic-0 {
668 hsic-1 {
[all …]
Dallwinner,sun8i-a83t-usb-phy.yaml37 - description: USB HSIC 12MHz clock
Dnvidia,tegra20-usb-phy.yaml105 enum: [utmi, ulpi, hsic]
Dnvidia,tegra194-xusb-padctl.yaml23 or high-speed USB (such as UTMI, ULPI and HSIC). The XUSB pad controller
/Documentation/devicetree/bindings/mfd/
Domap-usb-host.txt20 "ehci-hsic",
51 * "usb_host_hs_hsic480m_p1_clk" - Port 1 480MHz HSIC clock gate.
52 * "usb_host_hs_hsic480m_p2_clk" - Port 2 480MHz HSIC clock gate.
53 * "usb_host_hs_hsic480m_p3_clk" - Port 3 480MHz HSIC clock gate.
54 * "usb_host_hs_hsic60m_p1_clk" - Port 1 60MHz HSIC clock gate.
55 * "usb_host_hs_hsic60m_p2_clk" - Port 2 60MHz HSIC clock gate.
56 * "usb_host_hs_hsic60m_p3_clk" - Port 3 60MHz HSIC clock gate.
/Documentation/devicetree/bindings/usb/
Dusb.yaml40 serial is specified and High-Speed Inter-Chip feature if HSIC is
44 enum: [utmi, utmi_wide, ulpi, serial, hsic]
Dchipidea,usb2-imx.yaml144 const: hsic
258 # Example for HSIC:
270 phy_type = "hsic";
Dnvidia,tegra124-xusb.yaml103 - hsic-0
104 - hsic-1
Datmel-usb.txt44 "utmi", or "hsic".
Dnvidia,tegra186-xusb.yaml89 - hsic-0
Dnvidia,tegra210-xusb.yaml95 - hsic-0
Dchipidea,usb2-common.yaml139 In case of HSIC-mode, "idle" and "active" pin modes are mandatory.
/Documentation/devicetree/bindings/pinctrl/
Dqcom,msm8974-pinctrl.yaml87 tsif1, tsif2, hsic, grfc, audio_ref_clk, qua_mi2s, pri_mi2s,
162 hsic-state {
Dnvidia,tegra124-xusb-padctl.txt71 - ulpi-0, hsic-0, hsic-1:
Dqcom,apq8084-pinctrl.yaml85 hdmi_hpd, hdmi_rcv, hsic, ldo_en, ldo_update,
Dqcom,msm8960-pinctrl.yaml81 hdmi_ddc_clock, hdmi_ddc_data, hdmi_hot_plug_detect, hsic,
/Documentation/devicetree/bindings/soc/tegra/
Dnvidia,tegra20-pmc.yaml273 hsic, hv, lvds, mipi-bias, nand, pex-bias, pex-clk1, pex-clk2,
281 hdmi, hsic, lvds, mipi-bias, pex-bias, pex-clk1, pex-clk2, pex-cntrl,
340 dsic, dsid, hdmi, hsic, hv, lvds, mipi-bias, nand,
360 dsid, emmc, emmc2, gpio, hdmi, hsic, lvds, mipi-bias,
/Documentation/devicetree/bindings/arm/tegra/
Dnvidia,tegra186-pmc.yaml106 pex-clk1, usb0, usb1, usb2, usb-bias, uart, audio, hsic, dbg,
/Documentation/networking/device_drivers/cellular/qualcomm/
Drmnet.rst15 IP mode. Physical transports include USB, HSIC, PCIe and IP accelerator.