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/Documentation/devicetree/bindings/riscv/
Dcpus.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: RISC-V CPUs
10 - Paul Walmsley <paul.walmsley@sifive.com>
11 - Palmer Dabbelt <palmer@sifive.com>
12 - Conor Dooley <conor@kernel.org>
15 This document uses some terminology common to the RISC-V community
19 mandated by the RISC-V ISA: a PC and some registers. This
27 - $ref: /schemas/cpu.yaml#
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/Documentation/core-api/
Dcachetlb.rst2 Cache and TLB Flushing Under Linux
7 This document describes the cache/tlb flushing interfaces called
17 thinking SMP cache/tlb flushing must be so inefficient, this is in
23 First, the TLB flushing interfaces, since they are the simplest. The
24 "TLB" is abstracted under Linux as something the cpu uses to cache
25 virtual-->physical address translations obtained from the software
27 possible for stale translations to exist in this "TLB" cache.
44 the TLB. After running, this interface must make sure that
47 there will be no entries in the TLB for 'mm'.
57 address translations from the TLB. After running, this
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Ddma-api-howto.rst10 with example pseudo-code. For a concise description of the API, see
11 Documentation/core-api/dma-api.rst.
23 The virtual memory system (TLB, page tables, etc.) translates virtual
30 I/O devices use a third kind of address: a "bus address". If a device has
39 supports 64-bit addresses for main memory and PCI BARs, it may use an IOMMU
40 so devices only need to use 32-bit DMA addresses.
49 +-------+ +------+ +------+
52 C +-------+ --------> B +------+ ----------> +------+ A
54 +-----+ | | | | bridge | | +--------+
55 | | | | +------+ | | | |
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/Documentation/arch/arm/
Dinterrupts.rst5 2.5.2-rmk5:
7 major architecture-specific subsystems.
10 MMU TLB. Each MMU TLB variant is now handled completely separately -
11 we have TLB v3, TLB v4 (without write buffer), TLB v4 (with write buffer),
12 and finally TLB v4 (with write buffer, with I TLB invalidate entry).
14 allow more flexible TLB handling for the future.
26 SA1100 ------------> Neponset -----------> SA1111
28 -----------> USAR
30 -----------> SMC9196
33 exclusive of each other - if you're processing one interrupt from the
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/Documentation/arch/x86/
Dsva.rst1 .. SPDX-License-Identifier: GPL-2.0
19 application page-faults. For more information please refer to the PCIe
25 mmu_notifier() support to keep the device TLB cache and the CPU cache in
34 Unlike Single Root I/O Virtualization (SR-IOV), Scalable IOV (SIOV) permits
40 ID (PASID), which is a 20-bit number defined by the PCIe SIG.
43 IOMMU to track I/O on a per-PASID granularity in addition to using the PCIe
55 ENQCMD works with non-posted semantics and carries a status back if the
62 to perform I/O operations via use of PASID.
67 A new thread-scoped MSR (IA32_PASID) provides the connection between
69 accesses an SVA-capable device, this MSR is initialized with a newly
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/Documentation/translations/zh_CN/core-api/
Dcachetlb.rst1 .. include:: ../disclaimer-zh_CN.rst
3 :Original: Documentation/core-api/cachetlb.rst
14 .. _cn_core-api_cachetlb:
22 *译注:TLB,Translation Lookaside Buffer,页表缓存/变换旁查缓冲器*
35 用来缓存从软件页表获得的虚拟->物理地址转换的东西。这意味着,如果软件页
36 表发生变化,这个“TLB”缓存中就有可能出现过时(脏)的翻译。因此,当软件页表
58 这个接口必须确保以前对‘start’到‘end-1’范围内的地址空间‘vma->vm_mm’
60 ‘mm’的页表项用于‘start’到‘end-1’范围内的虚拟地址。
71 踪进程的mmap区域的支持结构体,地址空间可以通过vma->vm_mm获得。另
72 外,可以通过测试(vma->vm_flags & VM_EXEC)来查看这个区域是否是
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/Documentation/mm/
Dhighmem.rst12 High memory (highmem) is used when the size of physical memory approaches or
13 exceeds the maximum size of virtual memory. At that point it becomes
23 VM space so that we don't have to pay the full TLB invalidation costs for
30 +--------+ 0xffffffff
32 +--------+ 0xc0000000
36 +--------+ 0x00000000
39 time, but because we need virtual address space for other things - including
40 temporary maps to access the rest of the physical memory - the actual direct
54 * kmap_local_page(), kmap_local_folio() - These functions are used to create
64 These mappings are thread-local and CPU-local, meaning that the mapping
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Dpage_tables.rst1 .. SPDX-License-Identifier: GPL-2.0
10 feature of all Unix-like systems as time went by. In 1985 the feature was
34 As you can see, with 4KB pages the page base address uses bits 12-31 of the
42 this single table were referred to as *PTE*:s - page table entries.
57 megabytes or even gigabytes in a single high-level page table entry, taking
63 +-----+
65 +-----+
67 | +-----+
68 +-->| P4D |
69 +-----+
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/Documentation/virt/kvm/x86/
Dmmu.rst1 .. SPDX-License-Identifier: GPL-2.0
13 - correctness:
17 a particular implementation such as tlb size)
18 - security:
21 - performance:
23 - scaling:
25 - hardware:
27 - integration:
31 - dirty tracking:
33 and framebuffer-based displays
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/Documentation/arch/x86/x86_64/
Dboot-options.rst1 .. SPDX-License-Identifier: GPL-2.0
22 due to the shared banks, i.e. you might get duplicated
39 Do not opt-in to Local MCE delivery. Use legacy method
55 Don't overwrite the bios-set CMCI threshold. This boot option
62 Force-enable recoverable machine check code paths
73 Use IO-APIC. Default
76 Don't use the IO-APIC.
85 See Documentation/arch/x86/i386/IO-APIC.rst
91 Don't check the IO-APIC timer. This can work around
154 There are some built-in platform specific "quirks" - you may see:
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/Documentation/arch/sparc/
Dadi.rst19 2. Set TTE.mcd bit on any TLB entries that correspond to the range of
25 given tag for one ADI block size number of bytes. This step must
28 ADI block size for the platform is provided by the hypervisor to kernel
34 SPARC M7 processor, MMU uses bits 63-60 for version tags and ADI block
35 size is same as cacheline size which is 64 bytes. A task that sets ADI
37 virtual addresses that contain 0xa in bits 63-60.
43 ASI_MCD_PRIMARY or ASI_MCD_ST_BLKINIT_PRIMARY. ADI block size is
45 ADI block size to userspace using auxiliary vector along with other ADI
49 AT_ADI_BLKSZ ADI block size. This is the granularity and
58 - Version tag values of 0x0 and 0xf are reserved. These values match any
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/Documentation/networking/
Dbonding.rst1 .. SPDX-License-Identifier: GPL-2.0
11 Corrections, HA extensions: 2000/10/03-15:
13 - Willy Tarreau <willy at meta-x.org>
14 - Constantine Gavrilov <const-g at xpert.com>
15 - Chad N. Tindel <ctindel at ieee dot org>
16 - Janice Girouard <girouard at us dot ibm dot com>
17 - Jay Vosburgh <fubar at us dot ibm dot com>
22 - Mitch Williams <mitch.a.williams at intel.com>
35 the original tools from extreme-linux and beowulf sites will not work
119 -----------------------------------------------
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/Documentation/driver-api/
Dvfio.rst2 VFIO - "Virtual Function I/O" [1]_
6 to help ensure I/O devices behave within the boundaries they've been
7 allotted. This includes x86 hardware with AMD-Vi and Intel VT-d,
12 safe [2]_, non-privileged, userspace drivers.
16 I/O performance. From a device and host perspective, this simply
19 bare-metal device drivers [3]_.
22 field, also benefit from low-overhead, direct device access from
23 userspace. Examples include network adapters (often non-TCP/IP based)
36 ---------------------------
38 Devices are the main target of any I/O driver. Devices typically
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/Documentation/filesystems/
Dproc.rst1 .. SPDX-License-Identifier: GPL-2.0
24 1.1 Process-Specific Subdirectories
36 3 Per-Process Parameters
37 3.1 /proc/<pid>/oom_adj & /proc/<pid>/oom_score_adj - Adjust the oom-killer
39 3.2 /proc/<pid>/oom_score - Display current oom-killer score
40 3.3 /proc/<pid>/io - Display the IO accounting fields
41 3.4 /proc/<pid>/coredump_filter - Core dump filtering settings
42 3.5 /proc/<pid>/mountinfo - Information about mounts
44 3.7 /proc/<pid>/task/<tid>/children - Information about task children
45 3.8 /proc/<pid>/fdinfo/<fd> - Information about opened file
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/Documentation/virt/kvm/
Dapi.rst1 .. SPDX-License-Identifier: GPL-2.0
4 The Definitive KVM (Kernel-based Virtual Machine) API Documentation
13 - System ioctls: These query and set global attributes which affect the
17 - VM ioctls: These query and set attributes that affect an entire virtual
24 - vcpu ioctls: These query and set attributes that control the operation
32 - device ioctls: These query and set attributes that control the operation
80 facility that allows backward-compatible extensions to the API to be
104 the ioctl returns -ENOTTY.
122 -----------------------
139 -----------------
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/Documentation/arch/powerpc/
Dultravisor.rst1 .. SPDX-License-Identifier: GPL-2.0
16 (PVR=0x004e1203) or greater will be PEF-capable. A new ISA release
25 +------------------+
29 +------------------+
31 +------------------+
33 +------------------+
35 +------------------+
75 +---+---+---+---------------+
79 +---+---+---+---------------+
81 +---+---+---+---------------+
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/Documentation/arch/sparc/oradax/
Doracle-dax.rst25 the accompanying document, dax-hv-api.txt, which is a plain text
27 Specification" version 3.0.20+15, dated 2017-09-25.
86 made accessible via mmap(), and are read-only for the application.
109 equal to the number of bytes given in the call. Otherwise -1 is
113 -----------
122 --------
129 --------
138 ---------------------------------------------
140 A write() whose length is a multiple of the CCB size is treated as a
143 pwrite() system call. If -1 is returned then errno is set to indicate
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/Documentation/admin-guide/
Dkernel-parameters.txt16 force -- enable ACPI if default was off
17 on -- enable ACPI but allow fallback to DT [arm64,riscv64]
18 off -- disable ACPI if default was on
19 noirq -- do not use ACPI for IRQ routing
20 strict -- Be less tolerant of platforms that are not
22 rsdt -- prefer RSDT over (default) XSDT
23 copy_dsdt -- copy DSDT to memory
24 nospcr -- disable console in ACPI SPCR table as
41 If set to vendor, prefer vendor-specific driver
73 Documentation/firmware-guide/acpi/debug.rst for more information about
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/Documentation/RCU/
DRTFP.txt4 This document describes RCU-related publications, and is followed by
19 with short-lived threads, such as the K42 research operating system.
20 However, Linux has long-lived tasks, so more is needed.
23 serialization, which is an RCU-like mechanism that relies on the presence
27 that these overheads were not so expensive in the mid-80s. Nonetheless,
28 passive serialization appears to be the first deferred-destruction
30 has lapsed, so this approach may be used in non-GPL software, if desired.
34 In 1987, Rashid et al. described lazy TLB-flush [RichardRashid87a].
36 this paper helped inspire the update-side batching used in the later
38 a description of Argus that noted that use of out-of-date values can
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