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/Documentation/i2c/
Di2c-sysfs.rst1 .. SPDX-License-Identifier: GPL-2.0
4 Linux I2C Sysfs
10 I2C topology can be complex because of the existence of I2C MUX
11 (I2C Multiplexer). The Linux
12 kernel abstracts the MUX channels into logical I2C bus numbers. However, there
13 is a gap of knowledge to map from the I2C bus physical number and MUX topology
14 to logical I2C bus number. This doc is aimed to fill in this gap, so the
16 the concept of logical I2C buses in the kernel, by knowing the physical I2C
17 topology and navigating through the I2C sysfs in Linux shell. This knowledge is
18 useful and essential to use ``i2c-tools`` for the purpose of development and
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Dsummary.rst2 Introduction to I2C and SMBus
5 I²C (pronounce: I squared C and written I2C in the kernel documentation) is
6 a protocol developed by Philips. It is a two-wire protocol with variable
8 an inexpensive bus for connecting many types of devices with infrequent or
9 low bandwidth communications needs. I2C is widely used with embedded
11 and so are not advertised as being I2C but come under different names,
14 The latest official I2C specification is the `"I²C-bus specification and user
15 manual" (UM10204) <https://www.nxp.com/docs/en/user-guide/UM10204.pdf>`_
18 SMBus (System Management Bus) is based on the I2C protocol, and is mostly
19 a subset of I2C protocols and signaling. Many I2C devices will work on an
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Dinstantiating-devices.rst2 How to instantiate I2C devices
5 Unlike PCI or USB devices, I2C devices are not enumerated at the hardware
7 I2C bus segment, and what address these devices are using. For this
8 reason, the kernel code must instantiate I2C devices explicitly. There are
12 Method 1: Declare the I2C devices statically
13 --------------------------------------------
15 This method is appropriate when the I2C bus is a system bus as is the case
16 for many embedded systems. On such systems, each I2C bus has a number which
17 is known in advance. It is thus possible to pre-declare the I2C devices
18 which live on this bus.
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Di2c-address-translators.rst1 .. SPDX-License-Identifier: GPL-2.0
4 I2C Address Translators
11 -----------
13 An I2C Address Translator (ATR) is a device with an I2C slave parent
14 ("upstream") port and N I2C master child ("downstream") ports, and
16 with a modified slave address. The address used on the parent bus is
18 slave address of the child bus. Address translation is done by the
21 An ATR looks similar to an i2c-mux except:
22 - the address on the parent and child busses can be different
23 - there is normally no need to select the child port; the alias used on the
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Dslave-interface.rst2 Linux I2C slave interface description
5 by Wolfram Sang <wsa@sang-engineering.com> in 2014-15
7 Linux can also be an I2C slave if the I2C controller in use has slave
8 functionality. For that to work, one needs slave support in the bus driver plus
10 example for the latter is the slave-eeprom driver, which acts as a dual memory
11 driver. While another I2C master on the bus can access it like a regular
12 EEPROM, the Linux I2C slave can access the content via sysfs and handle data as
13 needed. The backend driver and the I2C bus driver communicate via events. Here
16 use a character device, be in-kernel only, or something completely different::
19 e.g. sysfs I2C slave events I/O registers
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Dgpio-fault-injection.rst2 Linux I2C fault injection
5 The GPIO based I2C bus master driver can be configured to provide fault
6 injection capabilities. It is then meant to be connected to another I2C bus
7 which is driven by the I2C bus master driver under test. The GPIO fault
8 injection driver can create special states on the bus which the other I2C bus
12 'i2c-fault-injector' subdirectory in the Kernel debugfs filesystem, usually
14 driven I2C bus. Each subdirectory will contain files to trigger the fault
15 injection. They will be described now along with their intended use-cases.
21 -----
26 because the bus master under test will not be able to clock. It should detect
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/Documentation/devicetree/bindings/i2c/
Di2c-demux-pinctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/i2c/i2c-demux-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Pinctrl-based I2C Bus Demultiplexer
10 - Wolfram Sang <wsa+renesas@sang-engineering.com>
13 This binding describes an I2C bus demultiplexer that uses pin multiplexing to
14 route the I2C signals, and represents the pin multiplexing configuration
15 using the pinctrl device tree bindings. This may be used to select one I2C
17 another I2C IP core on the SoC. The most simple example is to fall back to
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Daspeed,i2c.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/i2c/aspeed,i2c.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ASPEED I2C on the AST24XX, AST25XX, and AST26XX SoCs
10 - Rayn Chen <rayn_chen@aspeedtech.com>
13 - $ref: /schemas/i2c/i2c-controller.yaml#
18 - aspeed,ast2400-i2c-bus
19 - aspeed,ast2500-i2c-bus
20 - aspeed,ast2600-i2c-bus
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Di2c-arb-gpio-challenge.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/i2c/i2c-arb-gpio-challenge.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: GPIO-based I2C Arbitration Using a Challenge & Response Mechanism
10 - Doug Anderson <dianders@chromium.org>
11 - Peter Rosin <peda@axentia.se>
15 the master of an I2C bus in a multimaster situation.
18 standard I2C multi-master rules. Using GPIOs is generally useful in the case
19 where there is a device on the bus that has errata and/or bugs that makes
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Dnvidia,tegra186-bpmp-i2c.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/i2c/nvidia,tegra186-bpmp-i2c.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra186 (and later) BPMP I2C controller
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
15 owns certain HW devices, such as the I2C controller for the power
16 management I2C bus. Software running on other CPUs must perform IPC to
17 the BPMP in order to execute transactions on that I2C bus. This
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Di2c-mux-pinctrl.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/i2c/i2c-mux-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Pinctrl-based I2C Bus Mux
10 - Wolfram Sang <wsa@kernel.org>
13 This binding describes an I2C bus multiplexer that uses pin multiplexing to route the I2C
17 +-----+ +-----+
19 +------------------------+ +-----+ +-----+
21 | /----|------+--------+
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Di2c-mux.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/i2c/i2c-mux.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Common i2c bus multiplexer/switch properties.
10 - Peter Rosin <peda@axentia.se>
13 An i2c bus multiplexer/switch will have several child busses that are numbered
14 uniquely in a device dependent manner. The nodes for an i2c bus
15 multiplexer/switch will have one child node for each child bus.
17 For i2c multiplexers/switches that have child nodes that are a mixture of both
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Di2c-mux-gpmux.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/i2c/i2c-mux-gpmux.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: General Purpose I2C Bus Mux
10 - Peter Rosin <peda@axentia.se>
13 This binding describes an I2C bus multiplexer that uses a mux controller
14 from the mux subsystem to route the I2C signals.
16 .-----. .-----.
18 .------------. '-----' '-----'
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Di2c-mux-gpio.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/i2c/i2c-mux-gpio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: GPIO-based I2C Bus Mux
10 - Wolfram Sang <wsa@kernel.org>
13 This binding describes an I2C bus multiplexer that uses GPIOs to route the I2C signals.
15 +-----+ +-----+
17 +------------+ +-----+ +-----+
19 | | /--------+--------+
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Di2c-atr.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/i2c/i2c-atr.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Common i2c address translator properties
10 - Tomi Valkeinen <tomi.valkeinen@ideasonboard.com>
13 An I2C Address Translator (ATR) is a device with an I2C slave parent
14 ("upstream") port and N I2C master child ("downstream") ports, and
16 with a modified slave address. The address used on the parent bus is
18 slave address of the child bus. Address translation is done by the
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Dopencores,i2c-ocores.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/i2c/opencores,i2c-ocores.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: OpenCores I2C controller
10 - Peter Korsgaard <peter@korsgaard.com>
11 - Andrew Lunn <andrew@lunn.ch>
14 - $ref: /schemas/i2c/i2c-controller.yaml#
19 - items:
20 - enum:
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/Documentation/driver-api/
Di2c.rst4 I\ :sup:`2`\ C (or without fancy typography, "I2C") is an acronym for
5 the "Inter-IC" bus, a simple bus protocol which is widely used where low
7 some vendors use another name (such as "Two-Wire Interface", TWI) for
8 the same bus. I2C only needs two signals (SCL for clock, SDA for data),
10 I2C devices use seven bit addresses, and bus speeds of up to 400 kHz;
12 I2C is a multi-master bus; open drain signaling is used to arbitrate
16 The Linux I2C programming interfaces support the master side of bus
18 structured around two kinds of driver, and two kinds of device. An I2C
22 I2C bus segment it manages. On each I2C bus segment will be I2C devices
26 are functions to perform various I2C protocol operations; at this writing
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Dipmb.rst5 The Intelligent Platform Management Bus or IPMB, is an
6 I2C bus that provides a standardized interconnection between
10 IPMB bus.
15 hot-swapping disk drivers in the system chassis, etc...
27 ----------------------------
29 ipmb-dev-int - This is the driver needed on a Satellite MC to
31 This driver works with the I2C driver and a userspace
34 1) It is an I2C slave backend driver. So, it defines a callback
35 function to set the Satellite MC as an I2C slave.
43 --------------------
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/Documentation/devicetree/bindings/rtc/
Dtrivial-rtc.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/rtc/trivial-rtc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Alexandre Belloni <alexandre.belloni@bootlin.com>
18 - $ref: rtc.yaml#
23 # AB-RTCMC-32.768kHz-B5ZE-S3: Real Time Clock/Calendar Module with I2C Interface
24 - abracon,abb5zes3
25 # AB-RTCMC-32.768kHz-EOZ9: Real Time Clock/Calendar Module with I2C Interface
26 - abracon,abeoz9
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/Documentation/w1/slaves/
Dw1_ds28e17.rst7 * Maxim DS28E17 1-Wire-to-I2C Master Bridge
19 -----------
20 The DS28E17 is a Onewire slave device which acts as an I2C bus master.
22 This driver creates a new I2C bus for any DS28E17 device detected. I2C buses
23 come and go as the DS28E17 devices come and go. I2C slave devices connected to
25 connected to a "native" I2C bus master.
30 SUBSYSTEM=="i2c-dev", KERNEL=="i2c-[0-9]*", ATTRS{name}=="w1-19-*", \
31 SYMLINK+="i2c-$attr{name}"
33 may be used to create stable /dev/i2c- entries based on the unique id of the
40 This sets up the default I2C speed a DS28E17 get configured for as soon
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/Documentation/devicetree/bindings/soc/fsl/cpm_qe/cpm/
Di2c.txt1 * I2C
3 The I2C controller is expressed as a bus under the CPM node.
6 - compatible : "fsl,cpm1-i2c", "fsl,cpm2-i2c"
7 - reg : On CPM2 devices, the second resource doesn't specify the I2C
10 - #address-cells : Should be one. The cell is the i2c device address with
12 - #size-cells : Should be zero.
13 - clock-frequency : Can be used to set the i2c clock frequency. If
16 i2c drivers to find the bus to probe:
17 - linux,i2c-index : Can be used to hard code an i2c bus number. By default,
18 the bus number is dynamically assigned by the i2c core.
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/Documentation/translations/it_IT/i2c/
Dsummary.rst2 Introduzione a I2C e SMBus
5 I²C (letteralmente "I al quadrato C" e scritto I2C nella documentazione del
8 elevate (3.4 MHz). Questo protocollo offre un bus a basso costo per collegare
11 originali, per cui non sono indicati come I2C, ma hanno nomi diversi, per
14 L'ultima specifica ufficiale I2C è la `"Specifica I2C-bus e manuale utente"
20 https://www.nxp.com/docs/en/user-guide/UM10204.pdf>`_.
22 SMBus (Bus per la gestione del sistema) si basa sul protocollo I2C ed è
23 principalmente un sottoinsieme di protocolli e segnali I2C. Molti dispositivi
24 I2C funzioneranno su SMBus, ma alcuni protocolli SMBus aggiungono semantica
25 oltre quanto richiesto da I2C. Le moderne schede madri dei PC si affidano a
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/Documentation/devicetree/bindings/
Dunittest.txt6 - compatible: must be "unittest"
15 2) OF unittest i2c adapter platform device
20 - compatible: must be unittest-i2c-bus
22 Children nodes contain unittest i2c devices.
25 unittest-i2c-bus {
26 compatible = "unittest-i2c-bus";
29 3) OF unittest i2c device
31 ** I2C unittest device
34 - compatible: must be unittest-i2c-dev
39 unittest-i2c-dev {
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/Documentation/i2c/muxes/
Di2c-mux-gpio.rst2 Kernel driver i2c-mux-gpio
8 -----------
10 i2c-mux-gpio is an i2c mux driver providing access to I2C bus segments
11 from a master I2C bus and a hardware MUX controlled through GPIO pins.
15 ---------- ---------- Bus segment 1 - - - - -
16 | | SCL/SDA | |-------------- | |
17 | |------------| |
18 | | | | Bus segment 2 | |
19 | Linux | GPIO 1..N | MUX |--------------- Devices
20 | |------------| | | |
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/Documentation/driver-api/i3c/
Dprotocol.rst1 .. SPDX-License-Identifier: GPL-2.0
11 everything hardware related (like how things are transmitted on the bus, how
17 https://resources.mipi.org/mipi-i3c-v1-download).
22 The I3C (pronounced 'eye-three-see') is a MIPI standardized protocol designed
23 to overcome I2C limitations (limited speed, external signals needed for
24 interrupts, no automatic detection of the devices connected to the bus, ...)
25 while remaining power-efficient.
27 I3C Bus
30 An I3C bus is made of several I3C devices and possibly some I2C devices as
33 An I3C device on the I3C bus can have one of the following roles:
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