| /Documentation/devicetree/bindings/sound/ |
| D | allwinner,sun4i-a10-i2s.yaml | 4 $id: http://devicetree.org/schemas/sound/allwinner,sun4i-a10-i2s.yaml#
7 title: Allwinner A10 I2S Controller
19 - const: allwinner,sun4i-a10-i2s
20 - const: allwinner,sun6i-a31-i2s
21 - const: allwinner,sun8i-a83t-i2s
22 - const: allwinner,sun8i-h3-i2s
24 - const: allwinner,sun8i-r40-i2s
25 - const: allwinner,sun8i-h3-i2s
27 - const: allwinner,sun8i-v3-i2s
28 - const: allwinner,sun8i-h3-i2s
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| D | rockchip-i2s.yaml | 4 $id: http://devicetree.org/schemas/sound/rockchip-i2s.yaml#
7 title: Rockchip I2S controller
10 The I2S bus (Inter-IC sound bus) is a serial link for digital
22 - const: rockchip,rk3066-i2s
25 - rockchip,px30-i2s
26 - rockchip,rk1808-i2s
27 - rockchip,rk3036-i2s
28 - rockchip,rk3128-i2s
29 - rockchip,rk3188-i2s
30 - rockchip,rk3228-i2s
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| D | nvidia,tegra210-i2s.yaml | 4 $id: http://devicetree.org/schemas/sound/nvidia,tegra210-i2s.yaml#
7 title: Tegra210 I2S Controller
10 The Inter-IC Sound (I2S) controller implements full-duplex,
12 interfaces. It can interface with I2S compatible devices.
13 I2S controller can operate both in master and slave mode.
24 pattern: "^i2s@[0-9a-f]*$"
28 - const: nvidia,tegra210-i2s
31 - nvidia,tegra234-i2s
32 - nvidia,tegra194-i2s
33 - nvidia,tegra186-i2s
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| D | samsung-i2s.yaml | 4 $id: http://devicetree.org/schemas/sound/samsung-i2s.yaml#
7 title: Samsung SoC I2S controller
19 samsung,s3c6410-i2s: for 8/16/24bit stereo I2S.
21 samsung,s5pv210-i2s: for 8/16/24bit multichannel (5.1) I2S with
25 samsung,exynos5420-i2s: for 8/16/24bit multichannel (5.1) I2S for
32 samsung,exynos7-i2s: with all the available features of Exynos5 I2S.
33 Exynos7 I2S has 7.1 channel TDM support for capture, secondary FIFO
41 tesla,fsd-i2s: for 8/16/24bit stereo channel I2S for playback and
44 frequencies supported by Exynos7 I2S and 7.1 channel TDM support
49 - samsung,s3c6410-i2s
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| D | img,i2s-in.txt | 1 Imagination Technologies I2S Input Controller
5 - compatible : Compatible list, must contain "img,i2s-in"
19 "rx" Single DMA channel used by all active I2S channels
21 - img,i2s-channels : Number of I2S channels instantiated in the I2S in block
25 - interrupts : Contains the I2S in interrupts. Depending on
27 or an interrupt per I2S channel. For the case where there is
31 - resets: Contains a phandle to the I2S in reset signal
37 i2s_in: i2s-in@18100800 {
38 compatible = "img,i2s-in";
45 img,i2s-channels = <6>;
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| D | ingenic,aic.yaml | 7 title: Ingenic SoCs AC97 / I2S Controller (AIC)
22 - ingenic,jz4740-i2s
23 - ingenic,jz4760-i2s
24 - ingenic,jz4770-i2s
25 - ingenic,jz4780-i2s
26 - ingenic,x1000-i2s
28 - const: ingenic,jz4725b-i2s
29 - const: ingenic,jz4740-i2s
43 - description: I2S clock
48 - const: i2s
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| D | img,i2s-out.txt | 1 Imagination Technologies I2S Output Controller
5 - compatible : Compatible list, must contain "img,i2s-out"
20 "tx" Single DMA channel used by all active I2S channels
22 - img,i2s-channels : Number of I2S channels instantiated in the I2S out block
24 - resets: Contains a phandle to the I2S out reset signal
30 - interrupts : Contains the I2S out interrupts. Depending on
32 or an interrupt per I2S channel. For the case where there is
38 i2s_out: i2s-out@18100a00 {
39 compatible = "img,i2s-out";
47 img,i2s-channels = <6>;
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| D | rockchip-max98090.txt | 6 - rockchip,i2s-controller: The phandle of the Rockchip I2S controller that's
20 rockchip,model = "ROCKCHIP-I2S";
21 rockchip,i2s-controller = <&i2s>;
29 rockchip,model = "ROCKCHIP-I2S";
30 rockchip,i2s-controller = <&i2s>;
37 rockchip,model = "ROCKCHIP-I2S";
38 rockchip,i2s-controller = <&i2s>;
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| D | intel,keembay-i2s.yaml | 5 $id: http://devicetree.org/schemas/sound/intel,keembay-i2s.yaml#
8 title: Intel KeemBay I2S
15 Intel KeemBay I2S
23 - intel,keembay-i2s
25 - intel,keembay-hdmi-i2s
32 - description: I2S registers
33 - description: I2S gen configuration
37 - const: i2s-regs
79 i2s3: i2s@20140000 {
80 compatible = "intel,keembay-i2s";
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| D | nvidia,tegra30-i2s.yaml | 4 $id: http://devicetree.org/schemas/sound/nvidia,tegra30-i2s.yaml#
7 title: NVIDIA Tegra30 I2S controller
17 - nvidia,tegra124-i2s
18 - nvidia,tegra30-i2s
20 - const: nvidia,tegra114-i2s
21 - const: nvidia,tegra30-i2s
30 const: i2s
36 const: i2s
59 i2s@70080300 {
60 compatible = "nvidia,tegra30-i2s";
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| D | hisilicon,hi6210-i2s.txt | 1 * Hisilicon 6210 i2s controller
6 - "hisilicon,hi6210-i2s"
7 - reg: physical base address of the i2s controller unit and length of
9 - interrupts: should contain the i2s interrupt.
14 - "i2s-base"
25 Example for the hi6210 i2s controller:
27 i2s0: i2s@f7118000{
28 compatible = "hisilicon,hi6210-i2s";
29 reg = <0x0 0xf7118000 0x0 0x8000>; /* i2s unit */
33 clock-names = "dacodec", "i2s-base";
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| D | rockchip,i2s-tdm.yaml | 4 $id: http://devicetree.org/schemas/sound/rockchip,i2s-tdm.yaml#
7 title: Rockchip I2S/TDM Controller
10 The Rockchip I2S/TDM Controller is a Time Division Multiplexed
23 - rockchip,px30-i2s-tdm
24 - rockchip,rk1808-i2s-tdm
25 - rockchip,rk3308-i2s-tdm
26 - rockchip,rk3568-i2s-tdm
27 - rockchip,rk3588-i2s-tdm
28 - rockchip,rv1126-i2s-tdm
112 rockchip,i2s-rx-route:
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| D | xlnx,i2s.txt | 1 Device-Tree bindings for Xilinx I2S PL block
3 The IP supports I2S based playback/capture audio
6 - compatible: "xlnx,i2s-transmitter-1.0" for playback and
7 "xlnx,i2s-receiver-1.0" for capture
9 Required property common to both I2S playback and capture:
12 - xlnx,num-channels: Number of I2S streams. Can be any of 1, 2, 3, 4.
18 compatible = "xlnx,i2s-receiver-1.0";
24 compatible = "xlnx,i2s-transmitter-1.0";
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| D | nvidia,tegra20-i2s.yaml | 4 $id: http://devicetree.org/schemas/sound/nvidia,tegra20-i2s.yaml#
7 title: NVIDIA Tegra20 I2S Controller
10 The I2S Controller streams synchronous serial audio data between system
11 memory and an external audio device. The controller supports the I2S Left
20 const: nvidia,tegra20-i2s
29 const: i2s
66 i2s@70002800 {
67 compatible = "nvidia,tegra20-i2s";
72 reset-names = "i2s";
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| D | snps,designware-i2s.yaml | 4 $id: http://devicetree.org/schemas/sound/snps,designware-i2s.yaml#
7 title: DesignWare I2S controller
16 - const: canaan,k210-i2s
17 - const: snps,designware-i2s
19 - snps,designware-i2s
29 The interrupt line number for the I2S controller. Add this
30 parameter if the I2S controller that you are using does not
83 - description: I2S-rx enabled control offset of SYS_SYSCONSAIF__SYSCFG register.
84 - description: I2S-rx enabled control mask
86 The phandle to System Register Controller syscon node and the I2S-rx(ADC)
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| D | st,stm32-i2s.yaml | 4 $id: http://devicetree.org/schemas/sound/st,stm32-i2s.yaml#
7 title: STMicroelectronics STM32 SPI/I2S Controller
13 The SPI/I2S block supports I2S/PCM protocols when configured on I2S mode.
14 Only some SPI instances support I2S.
22 - st,stm32h7-i2s
34 - description: I2S parent clock for sampling rates multiple of 8kHz.
35 - description: I2S parent clock for sampling rates multiple of 11.025kHz.
61 description: Configure the I2S device as MCLK clock provider.
89 compatible = "st,stm32h7-i2s";
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| D | cirrus,ep9301-i2s.yaml | 4 $id: http://devicetree.org/schemas/sound/cirrus,ep9301-i2s.yaml#
7 title: Cirrus EP93xx I2S Controller
10 The I2S controller is used to stream serial audio data between the external
11 I2S CODECs’, ADCs/DACs, and the ARM Core. The controller supports I2S, Left-
22 const: cirrus,ep9301-i2s
68 i2s: i2s@80820000 {
69 compatible = "cirrus,ep9301-i2s";
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| D | google,chv3-i2s.yaml | 4 $id: http://devicetree.org/schemas/sound/google,chv3-i2s.yaml#
7 title: Google Chameleon v3 I2S device
13 I2S device for the Google Chameleon v3. The device handles both RX
18 const: google,chv3-i2s
39 i2s@c0060300 {
40 compatible = "google,chv3-i2s";
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| D | rockchip-rt5645.txt | 6 - rockchip,i2s-controller: The phandle of the Rockchip I2S controller that's
14 rockchip,model = "ROCKCHIP-I2S";
15 rockchip,i2s-controller = <&i2s>;
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| D | cdns,xtfpga-i2s.txt | 1 Bindings for I2S controller built into xtfpga Xtensa bitstreams.
4 - compatible: shall be "cdns,xtfpga-i2s".
7 - clocks: phandle to the clk used as master clock. I2S bus clock
12 i2s0: xtfpga-i2s@d080000 {
14 compatible = "cdns,xtfpga-i2s";
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| D | mikroe,mikroe-proto.txt | 5 - dai-format: Must be "i2s".
6 - i2s-controller: The phandle of the I2S controller.
19 i2s-controller = <&i2s0>;
21 dai-format = "i2s";
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| D | adi,axi-i2s.txt | 1 ADI AXI-I2S controller
7 - compatible : Must be "adi,axi-i2s-1.00.a"
8 - reg : Must contain I2S core's registers location and length
27 i2s: i2s@77600000 {
28 compatible = "adi,axi-i2s-1.00.a";
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| D | nxp,lpc3220-i2s.yaml | 4 $id: http://devicetree.org/schemas/sound/nxp,lpc3220-i2s.yaml#
7 title: NXP LPC32XX I2S Controller
10 The I2S controller in LPC32XX SoCs, ASoC DAI.
22 - nxp,lpc3220-i2s
63 i2s@20094000 {
64 compatible = "nxp,lpc3220-i2s";
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| D | atmel,sama5d2-i2s.yaml | 5 $id: http://devicetree.org/schemas/sound/atmel,sama5d2-i2s.yaml#
8 title: Atmel I2S controller
16 Atmel I2S (Inter-IC Sound Controller) bus is the standard
21 const: atmel,sama5d2-i2s
33 - description: I2S mux clock (Optional). Set
70 i2s@f8050000 {
71 compatible = "atmel,sama5d2-i2s";
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| /Documentation/devicetree/bindings/clock/ |
| D | qcom,lcc.yaml | 58 - description: Mic I2S codec clock
59 - description: Mic I2S spare clock
60 - description: Speaker I2S codec clock
61 - description: Speaker I2S spare clock
92 - description: Mic I2S codec clock
93 - description: Mic I2S spare clock
94 - description: Speaker I2S codec clock
95 - description: Speaker I2S spare clock
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