| /Documentation/devicetree/bindings/powerpc/opal/ |
| D | power-mgt.txt | 5 idle states. The description of these idle states is exposed via the
10 Typically each idle state has the following associated properties:
12 - name: The name of the idle state as defined by the firmware.
14 - flags: indicating some aspects of this idle states such as the
16 idle states and so on. The flag bits are as follows:
19 CPU from idle to running.
22 this idle state in order to accrue power-savings
27 The following properties provide details about the idle states. These
29 provides the value of that property for the idle state associated with
32 If idle-states are defined, then the properties
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| /Documentation/admin-guide/pm/ |
| D | cpuidle.rst | 8 CPU Idle Time Management
21 memory or executed. Those states are the *idle* states of the processor.
23 Since part of the processor hardware is not used in idle states, entering them
27 CPU idle time management is an energy-efficiency feature concerned about using
28 the idle states of processors for this purpose.
33 CPU idle time management operates on CPUs as seen by the *CPU scheduler* (that
44 enter an idle state, that applies to the processor as a whole.
52 enter an idle state, that applies to the core that asked for it in the first
56 except for one have been put into idle states at the "core level" and the
57 remaining core asks the processor to enter an idle state, that may trigger it
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| D | intel_idle.rst | 5 ``intel_idle`` CPU Idle Time Management Driver
17 :doc:`CPU idle time management subsystem <cpuidle>` in the Linux kernel
18 (``CPUIdle``). It is the default CPU idle time management driver for the
27 logical CPU executing it is idle and so it may be possible to put some of the
42 .. _intel-idle-enumeration-of-states:
44 Enumeration of Idle States
50 as C-states (in the ACPI terminology) or idle states. The list of meaningful
51 ``MWAIT`` hint values and idle states (i.e. low-power configurations of the
55 In order to create a list of available idle states required by the ``CPUIdle``
56 subsystem (see :ref:`idle-states-representation` in
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| D | suspend-flows.rst | 27 significant differences between the :ref:`suspend-to-idle <s2idle>` code flows
42 Suspend-to-idle Suspend Code Flow
46 state to the :ref:`suspend-to-idle <s2idle>` sleep state:
101 When all devices have been suspended, CPUs enter the idle loop and are put
102 into the deepest available idle state. While doing that, each of them
106 The last CPU to enter the idle state also stops the timekeeping which
109 That allows the CPUs to stay in the deep idle state relatively long in one
113 interrupts. If that happens, they go back to the idle state unless the
120 Suspend-to-idle Resume Code Flow
124 :ref:`suspend-to-idle <s2idle>` sleep state into the working state:
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| /Documentation/devicetree/bindings/memory-controllers/ |
| D | rockchip,rk3399-dmc.yaml | 60 Configure the PD_IDLE value. Defines the power-down idle period in which
61 memories are placed into power-down mode if bus is idle for PD_IDLE DFI
63 See also rockchip,pd-idle-ns.
69 Configure the SR_IDLE value. Defines the self-refresh idle period in
70 which memories are placed into self-refresh mode if bus is idle for
72 See also rockchip,sr-idle-ns.
79 Defines the memory self-refresh and controller clock gating idle period.
81 arg gating started if bus is idle for sr_mc_gate_idle*1024 DFI clock
83 See also rockchip,sr-mc-gate-idle-ns.
89 Defines the self-refresh power down idle period in which memories are
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| /Documentation/devicetree/bindings/power/ |
| D | domain-idle-state.yaml | 4 $id: http://devicetree.org/schemas/power/domain-idle-state.yaml#
7 title: PM Domain Idle States
13 A domain idle state node represents the state parameters that will be used to
18 const: domain-idle-states
25 Each state node represents a domain idle state description.
29 const: domain-idle-state
33 The worst case latency in microseconds required to enter the idle
39 The worst case latency in microseconds required to exit the idle
44 The minimum residency duration in microseconds after which the idle
46 entering the idle state.
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| D | power-domain.yaml | 31 domain-idle-states:
36 Phandles of idle states that defines the available states for the
37 power-domain provider. The idle state definitions are compatible with the
38 domain-idle-state bindings, specified in ./domain-idle-state.yaml.
40 Note that, the domain-idle-state property reflects the idle states of this
41 PM domain and not the idle states of the devices or sub-domains in the PM
42 domain. Devices and sub-domains have their own idle states independent of
43 the parent domain's idle states. In the absence of this property, the
110 domain-idle-states = <&DOMAIN_RET>, <&DOMAIN_PWR_DN>;
118 domain-idle-states = <&DOMAIN_PWR_DN>;
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| /Documentation/admin-guide/thermal/ |
| D | intel_powerclamp.rst | 15 - Idle Injection
46 idle injection across all online CPU threads was introduced. The goal
57 Idle Injection
70 If the kernel can also inject idle time to the system, then a
73 control system, where the target set point is a user-selected idle
75 between the actual package level C-state residency ratio and the target idle
83 thread synchronizes its idle time and duration, based on the rounding
91 Alignment of idle time around jiffies ensures scalability for HZ
94 kidle_inject/cpu. During idle injection, it runs monitor/mwait idle
98 The NOHZ schedule tick is disabled during idle time, but interrupts
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| /Documentation/devicetree/bindings/cpu/ |
| D | idle-states.yaml | 4 $id: http://devicetree.org/schemas/cpu/idle-states.yaml#
7 title: Idle states
21 representing the range of dynamic idle states that a processor can enter at
23 parameters required to enter/exit specific idle states on a given processor.
26 2 - ARM idle states
40 PM implementation to put the processor in different idle states (which include
41 states listed above; "off" state is not an idle state since it does not have
44 Idle state parameters (e.g. entry latency) are platform specific and need to
48 The device tree binding definition for ARM idle states is the subject of this
52 3 - RISC-V idle states
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| /Documentation/driver-api/pm/ |
| D | cpuidle.rst | 5 CPU Idle Time Management
13 CPU Idle Time Management Subsystem
18 cores) is idle after an interrupt or equivalent wakeup event, which means that
19 there are no tasks to run on it except for the special "idle" task associated
21 belongs to. That can be done by making the idle logical CPU stop fetching
23 depended on by it into an idle state in which they will draw less power.
25 However, there may be multiple different idle states that can be used in such a
28 particular idle state. That is the role of the CPU idle time management
35 units: *governors* responsible for selecting idle states to ask the processor
40 CPU Idle Time Governors
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| /Documentation/driver-api/thermal/ |
| D | cpu-idle-cooling.rst | 4 CPU Idle Cooling
37 decrease. Acting on the idle state duration or the idle cycle
47 At a specific OPP, we can assume that injecting idle cycle on all CPUs
49 idle state target residency, we lead to dropping the static and the
51 this state). So the sustainable power with idle cycles has a linear
57 Idle Injection:
60 The base concept of the idle injection is to force the CPU to go to an
61 idle state for a specified time each control cycle, it provides
64 their idle cycles synchronously, the cluster can reach its power down
66 to almost zero. However, these idle cycles injection will add extra
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| /Documentation/devicetree/bindings/thermal/ |
| D | thermal-idle.yaml | 5 $id: http://devicetree.org/schemas/thermal/thermal-idle.yaml#
8 title: Thermal idle cooling device
14 The thermal idle cooling device allows the system to passively
15 mitigate the temperature on the device by injecting idle cycles,
18 This binding describes the thermal idle node.
22 const: thermal-idle
24 A thermal-idle node describes the idle cooling device properties to
36 The idle duration in microsecond the device should cool down.
40 The exit latency constraint in microsecond for the injected idle state
42 idle state from among all the present ones.
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| /Documentation/admin-guide/mm/ |
| D | idle_page_tracking.rst | 2 Idle Page Tracking
8 The idle page tracking feature allows to track which memory pages are being
9 accessed by a workload and which are idle. This information can be useful for
21 The idle page tracking API is located at ``/sys/kernel/mm/page_idle``.
28 set, the corresponding page is idle.
30 A page is considered idle if it has not been accessed since it was marked idle
33 To mark a page idle one has to set the bit corresponding to
39 page types (e.g. SLAB pages) an attempt to mark a page idle is silently ignored,
40 and hence such pages are never reported idle.
42 For huge pages the idle flag is set only on the head page, so one has to read
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| /Documentation/devicetree/bindings/mux/ |
| D | mux-controller.yaml | 33 have when it is idle. The idle-state property is used for this. If the
34 idle-state is not present, the mux controller is typically left as is when
35 it is idle. For multiplexer chips that expose several mux controllers, the
36 idle-state property is an array with one idle state for each mux controller.
39 as is when it is idle. This is the default, but can still be useful for
41 there is a need to "step past" a mux controller and set some other idle
45 multiplexer. Using this disconnected high-impedance state as the idle state
46 is indicated with idle state (-2).
62 idle-state = <MUX_IDLE_DISCONNECT MUX_IDLE_AS_IS 2>;
85 idle-state:
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| D | adi,adg792a.txt | 18 - idle-state : if present, array of states that the mux controllers will have
19 when idle. The special state MUX_IDLE_AS_IS is the default and
28 * Mux 0 is disconnected when idle, mux 1 idles in the previously
37 idle-state = <MUX_IDLE_DISCONNECT MUX_IDLE_AS_IS 1>;
63 idle-state = <1>;
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| D | adi,adgs1408.txt | 18 - idle-state : if present, the state that the mux controller will have
19 when idle. The special state MUX_IDLE_AS_IS is the default and
29 * Mux state set to idle as is (no idle-state declared)
|
| /Documentation/timers/ |
| D | no_hz.rst | 19 2. Omit scheduling-clock ticks on idle CPUs (CONFIG_NO_HZ_IDLE=y or
23 3. Omit scheduling-clock ticks on CPUs that are either idle or that
40 that use short bursts of CPU, where there are very frequent idle
41 periods, but where these idle periods are also quite short (tens or
46 other than increasing the overhead of switching to and from idle and
52 However, if you are instead running a light workload with long idle
65 Omit Scheduling-Clock Ticks For Idle CPUs
68 If a CPU is idle, there is little point in sending it a scheduling-clock
71 and an idle CPU has no duties to shift its attention among.
73 An idle CPU that is not receiving scheduling-clock interrupts is said to
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| /Documentation/scheduler/ |
| D | sched-stats.rst | 55 4) # of times schedule() left the processor idle
81 of idleness (idle, busy, and newly idle):
84 cpu was idle
86 the load did not require balancing when the cpu was idle
88 more tasks and failed, when the cpu was idle
90 sched_balance_rq() in this domain when the cpu was idle
92 was idle
94 the target task was cache-hot when idle
96 not find a busier queue while the cpu was idle
98 cpu was idle but no busier group was found
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| /Documentation/devicetree/bindings/mfd/ |
| D | twl4030-power.txt | 11 "ti,twl4030-power-idle"
12 "ti,twl4030-power-idle-osc-off"
17 When using ti,twl4030-power-idle, the TI recommended configuration
18 for idle modes is loaded to the tlw4030 PMIC.
20 When using ti,twl4030-power-idle-osc-off, the TI recommended
22 down during off-idle. Note that this does not work on all boards
|
| /Documentation/devicetree/bindings/i2c/ |
| D | i2c-mux-pinctrl.yaml | 34 The only exception is that no bus will be created for a state named "idle". If such a state is
37 pinctrl-names = "ddc", "pta", "idle" -> ddc = bus 0, pta = bus 1
38 pinctrl-names = "ddc", "idle", "pta" -> Invalid ("idle" not last)
39 pinctrl-names = "idle", "ddc", "pta" -> Invalid ("idle" not last)
44 If an idle state is defined, whenever an access is not being made to a device on a child bus,
45 the idle pinctrl state will be programmed into hardware.
47 If an idle state is not defined, the most recently used pinctrl state will be left programmed
77 pinctrl-names = "ddc", "pta", "idle";
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| D | i2c-mux-reg.txt | 23 - idle-state: value to set the muxer to when idle. When no value is
29 If an idle state is defined, using the idle-state (optional) property,
31 register will be set according to the idle value.
33 If an idle state is not defined, the most recently used value will be
|
| /Documentation/devicetree/bindings/arm/ |
| D | psci.yaml | 95 idle state nodes with entry-method property is set to "psci", as per
98 [1] Kernel documentation - ARM idle states bindings
99 Documentation/devicetree/bindings/cpu/idle-states.yaml
113 For these cases, the definitions of the idle states for the CPUs and the
114 CPU topology, must conform to the binding in [3]. The idle states
124 [4] Documentation/devicetree/bindings/power/domain-idle-state.yaml
188 // Case 4: CPUs and CPU idle states described using the hierarchical model.
212 idle-states {
215 compatible = "arm,idle-state";
223 domain-idle-states {
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| /Documentation/admin-guide/hw-vuln/ |
| D | core-scheduling.rst | 102 The idle task is considered special, as it trusts everything and everything
110 the idle task is selected. Idle task is globally trusted.
114 switch to the new task immediately. If an idle task is selected for a sibling,
115 then the sibling is considered to be in a `forced idle` state. I.e., it may
116 have tasks on its on runqueue to run, however it will still have to run idle.
127 task. If a sibling does not have a trusted task to run, it will be forced idle
128 by the scheduler (idle thread is scheduled to run).
131 the sibling to force it into idle. This results in 4 cases which need to be
136 A idle -> user space user space -> idle
137 B idle -> user space guest -> idle
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| /Documentation/devicetree/bindings/watchdog/ |
| D | atmel,sama5d4-wdt.yaml | 46 atmel,idle-halt:
49 present if you want to stop the watchdog when the CPU is in idle state.
51 watchdog not counting when the CPU is in idle state, therefore the
53 if the CPU stop working while it is in idle state, which is probably
78 atmel,idle-halt;
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| /Documentation/trace/ |
| D | events-nmi.rst | 41 …<idle>-0 [000] d.h3 505.397558: nmi_handler: perf_event_nmi_handler() delta_ns: 3236765 hand…
42 …<idle>-0 [000] d.h3 505.805893: nmi_handler: perf_event_nmi_handler() delta_ns: 3174234 hand…
43 …<idle>-0 [000] d.h3 506.158206: nmi_handler: perf_event_nmi_handler() delta_ns: 3084642 hand…
44 …<idle>-0 [000] d.h3 506.334346: nmi_handler: perf_event_nmi_handler() delta_ns: 3080351 hand…
|