Home
last modified time | relevance | path

Searched +full:input +full:- +full:ngpios (Results 1 – 10 of 10) sorted by relevance

/Documentation/devicetree/bindings/gpio/
Dnuvoton,sgpio.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jim LIU <JJLIU0@nuvoton.com>
20 to 64 output pins, and up to 64 input pins, the pin is only for GPI or GPO.
22 - Support interrupt option for each input port and various interrupt
23 sensitivity options (level-high, level-low, edge-high, edge-low)
24 - ngpios is number of nuvoton,input-ngpios GPIO lines and nuvoton,output-ngpios GPIO lines.
25 nuvoton,input-ngpios GPIO lines is only for GPI.
26 nuvoton,output-ngpios GPIO lines is only for GPO.
[all …]
Daspeed,sgpio.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Andrew Jeffery <andrew@aj.id.au>
17 - Support interrupt option for each input port and various interrupt
18 sensitivity option (level-high, level-low, edge-high, edge-low)
19 - Support reset tolerance option for each output port
20 - Directly connected to APB bus and its shift clock is from APB bus clock
22 - Co-work with external signal-chained TTL components (74LV165/74LV595)
27 - aspeed,ast2400-sgpio
[all …]
Dgpio-ts4900.txt1 * Technologic Systems I2C-FPGA's GPIO controller bindings
4 TS-4900's FPGA encodes the GPIO state on 3 bits, whereas the TS-7970's FPGA
5 uses 2 bits: it doesn't use a dedicated input bit.
8 - compatible: Should be one of the following
9 "technologic,ts4900-gpio"
10 "technologic,ts7970-gpio"
11 - reg: Physical base address of the controller and length
13 - #gpio-cells: Should be two. The first cell is the pin number.
14 - gpio-controller: Marks the device node as a gpio controller.
17 - ngpios: Number of GPIOs this controller is instantiated with,
[all …]
Dgpio-pisosr.txt1 Generic Parallel-in/Serial-out Shift Register GPIO Driver
3 This binding describes generic parallel-in/serial-out shift register
4 devices that can be used for GPI (General Purpose Input). This includes
5 SN74165 serial-out shift registers and the SN65HVS88x series of
9 - compatible : Should be "pisosr-gpio".
10 - gpio-controller : Marks the device node as a GPIO controller.
11 - #gpio-cells : Should be two. For consumer use see gpio.txt.
14 - ngpios : Number of used GPIO lines (0..n-1), default is 8.
15 - load-gpios : GPIO pin specifier attached to load enable, this
17 load input pin values into the device.
[all …]
Dgpio.txt5 -----------------
7 GPIO properties should be named "[<name>-]gpios", with <name> being the purpose
8 of this GPIO for the device. While a non-existent <name> is considered valid
10 for new bindings. Also, GPIO properties named "[<name>-]gpio" are valid and old
24 and bit-banged data signals:
27 gpio-controller;
28 #gpio-cells = <2>;
32 data-gpios = <&gpio1 12 0>,
44 recommended to use the two-cell approach.
48 include/dt-bindings/gpio/gpio.h whenever possible:
[all …]
/Documentation/devicetree/bindings/pinctrl/
Dmicrochip,sparx5-sgpio.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/microchip,sparx5-sgpio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lars Povlsen <lars.povlsen@microchip.com>
21 pattern: "^gpio@[0-9a-f]+$"
25 - microchip,sparx5-sgpio
26 - mscc,ocelot-sgpio
27 - mscc,luton-sgpio
29 "#address-cells":
[all …]
Dintel,pinctrl-keembay.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/intel,pinctrl-keembay.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lakshmi Sowjanya D <lakshmi.sowjanya.d@intel.com>
14 of pin directions, input/output values and configuration
19 const: intel,keembay-pinctrl
24 gpio-controller: true
26 '#gpio-cells':
29 ngpios:
[all …]
Dst,stm32-pinctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/pinctrl/st,stm32-pinctrl.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Alexandre TORGUE <alexandre.torgue@foss.st.com>
15 controller. It controls the input/output settings on the available pins and
17 on-chip controllers onto these pads.
22 - st,stm32f429-pinctrl
23 - st,stm32f469-pinctrl
24 - st,stm32f746-pinctrl
[all …]
/Documentation/admin-guide/gpio/
Dgpio-sim.rst1 .. SPDX-License-Identifier: GPL-2.0-or-later
6 The configfs GPIO Simulator (gpio-sim) provides a way to create simulated GPIO
12 ------------------------
14 The gpio-sim module registers a configfs subsystem called ``'gpio-sim'``. For
21 **Group:** ``/config/gpio-sim``
23 This is the top directory of the gpio-sim configfs tree.
25 **Group:** ``/config/gpio-sim/gpio-device``
27 **Attribute:** ``/config/gpio-sim/gpio-device/dev_name``
29 **Attribute:** ``/config/gpio-sim/gpio-device/live``
32 attribute is read-only and allows the user-space to read the platform device
[all …]
/Documentation/devicetree/bindings/arm/marvell/
Dap80x-system-controller.txt6 registers giving access to numerous features: clocks, pin-muxing and
11 - compatible: must be: "syscon", "simple-mfd";
12 - reg: register area of the AP80x system controller
18 -------
24 - 0: reference clock of CPU cluster 0
25 - 1: reference clock of CPU cluster 1
26 - 2: fixed PLL at 1200 Mhz
27 - 3: MSS clock, derived from the fixed PLL
31 - compatible: must be one of:
32 * "marvell,ap806-clock"
[all …]