Searched full:instructions (Results 1 – 25 of 204) sorted by relevance
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| /Documentation/arch/arm64/ |
| D | legacy_instructions.rst | 2 Legacy instructions
6 emulation of instructions which have been deprecated, or obsoleted in
18 Generates undefined instruction abort. Default for instructions that
27 instructions, .e.g., CP15 barriers
34 instructions. Using hardware execution generally provides better
36 about the use of the deprecated instructions.
39 architecture. Deprecated instructions should default to emulation
40 while obsolete instructions must be undefined by default.
45 Supported legacy instructions
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| D | pointer-authentication.rst | 25 The extension adds instructions to insert a valid PAC into a pointer,
30 A subset of these instructions have been allocated from the HINT
32 these instructions behave as NOPs. Applications and libraries using
33 these instructions operate correctly regardless of the presence of the
57 with HINT space pointer authentication instructions protecting
107 register. Any attempt to use the Pointer Authentication instructions will
128 instructions to sign and authenticate function pointers and other pointers
135 but before executing any PAC instructions.
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| /Documentation/devicetree/bindings/riscv/ |
| D | extensions.yaml | 86 The standard A extension for atomic instructions, as ratified in the
109 The standard C extension for compressed instructions, as ratified in
183 The Zacas extension for Atomic Compare-and-Swap (CAS) instructions
197 acceleration instructions as ratified at commit 6d33919 ("Merge pull
215 The standard Zbkb bitmanip instructions for cryptography as ratified
221 The standard Zbkc carry-less multiply instructions as ratified
227 The standard Zbkx crossbar permutation instructions as ratified
234 instructions as ratified at commit 6d33919 ("Merge pull request #158
241 RV64 as it contains no instructions") of riscv-code-size-reduction,
249 RV64 as it contains no instructions") of riscv-code-size-reduction,
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| /Documentation/bpf/standardization/ |
| D | instruction-set.rst | 33 mnemonic functions when describing the semantics of instructions.
120 An implementation does not need to support all instructions specified in this
121 document (e.g., deprecated instructions). Instead, a number of conformance
124 conformance group means it MUST support all instructions in that conformance
128 that executes instructions, and tools such as compilers that generate
129 instructions for the runtime. Thus, capability discovery in terms of
133 corresponds to a set of instructions that are mandatory. That is, each
138 * base32: includes all instructions defined in this
140 * base64: includes base32, plus instructions explicitly noted
142 * atomic32: includes 32-bit atomic operation instructions (see `Atomic operations`_).
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| /Documentation/bpf/ |
| D | linux-notes.rst | 10 Byte swap instructions
15 Jump instructions
45 Legacy BPF Packet access instructions
49 <instruction-set.html#legacy-bpf-packet-access-instructions>`_,
50 Linux has special eBPF instructions for access to packet data that have been
54 The instructions come in two forms: ``BPF_ABS | <size> | BPF_LD`` and
57 These instructions are used to access packet data and can only be used when
63 These instructions have seven implicit operands:
72 These instructions have an implicit program exit condition as well. If an
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| D | bpf_design_QA.rst | 93 It's the maximum number of instructions that the unprivileged bpf
95 Like the maximum number of instructions that can be explored during
98 of 1 million NOP instructions. There is a limit to the maximum number
119 Q: LD_ABS and LD_IND instructions vs C code
129 Q: BPF instructions mapping not one-to-one to native CPU
131 Q: It seems not all BPF instructions are one-to-one to native CPU.
149 of LD_ABS insn). Those instructions need to invoke epilogue and
152 Q: Why BPF_JLT and BPF_JLE instructions were not introduced in the beginning?
156 due to lack of these compare instructions and they were added.
157 These two instructions is a perfect example what kind of new BPF
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| D | clang-notes.rst | 17 Arithmetic instructions
23 Jump instructions
32 Clang can generate atomic instructions by default when ``-mcpu=v3`` is
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| /Documentation/arch/arm/ |
| D | kernel_mode_neon.rst | 7 * Use only NEON instructions, or VFP instructions that don't rely on support
19 It is possible to use NEON instructions (and in some cases, VFP instructions) in
24 may call schedule()], as NEON or VFP instructions will be executed in a
43 should be called before any kernel mode NEON or VFP instructions are issued.
74 Such software assistance is currently not implemented for VFP instructions
82 kernel_neon_end(), i.e., that it is only allowed to issue NEON/VFP instructions
84 instructions of its own at -O3 level if -mfpu=neon is selected, and even if the
86 instructions appearing in unexpected places if no special care is taken.
98 both NEON and VFP instructions will only ever appear in designated compilation
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| D | swp_emulation.rst | 4 ARMv6 architecture deprecates use of the SWP/SWPB instructions, and recommends
5 moving to the load-locked/store-conditional instructions LDREX and STREX.
8 instructions, triggering an undefined instruction exception when executed.
9 Trapped instructions are emulated using an LDREX/STREX or LDREXB/STREXB
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| /Documentation/arch/x86/x86_64/ |
| D | fsgs.rst | 6 The x86 architecture supports segmentation. Instructions which access
69 Accessing FS/GS base with the FSGSBASE instructions
73 instructions to access the FS and GS base registers directly from user
74 space. These instructions are also supported on AMD Family 17H CPUs. The
75 following instructions are available:
84 The instructions avoid the overhead of the arch_prctl() syscall and allow
90 FSGSBASE instructions enablement
92 The instructions are enumerated in CPUID leaf 7, bit 0 of EBX. If
95 The availability of the instructions does not enable them
103 instructions will fault with a #UD exception.
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| D | fred.rst | 24 delivery and, for returning from events, two FRED return instructions.
29 event delivery and the FRED return instructions are FRED transitions.
61 FRED allows explicit unblock of NMI with new event return instructions
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| /Documentation/virt/ |
| D | paravirt_ops.rst | 16 corresponding to low-level critical instructions and high-level
28 Usually these operations correspond to low-level critical instructions. They
34 because they include sensitive instructions or some code paths in
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| /Documentation/virt/kvm/ |
| D | ppc-pv.rst | 9 instructions and can emulate them accordingly.
12 instructions that needlessly return us to the hypervisor even though they
15 This is what the PPC PV interface helps with. It takes privileged instructions
35 'hypercall-instructions'. This property contains at most 4 opcodes that make
36 up the hypercall. To call a hypercall, just call these instructions.
138 Patched instructions
141 The "ld" and "std" instructions are transformed to "lwz" and "stw" instructions
147 also act on the shared page. So calling privileged instructions still works as
187 Some instructions require more logic to determine what's going on than a load
189 RAM around where we can live translate instructions to. What happens is the
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| /Documentation/arch/arm/nwfpe/ |
| D | netwinder-fpe.rst | 9 instructions. It follows the conventions in the ARM manual.
19 Floating Point Coprocessor Data Transfer Instructions (CPDT)
28 These instructions are fully implemented.
40 These instructions are fully implemented. They store/load three words
46 Floating Point Coprocessor Register Transfer Instructions (CPRT)
49 Conversions, read/write status/control register instructions
62 RFC/WFC are fully implemented. RFC/WFC are supervisor only instructions, and
66 Compare instructions
75 Floating Point Coprocessor Data Instructions (CPDT)
95 equivalent to the MUF/DVF/RDV instructions. This is acceptable according
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| /Documentation/arch/powerpc/ |
| D | elf_hwcaps.rst | 48 The Power ISA uses the term "facility" to describe a class of instructions,
52 instructions that can be used differ between the v3.0B and v3.1B ISA
59 classes of instructions and operating modes which may be optional or
97 The processor has a unified L1 cache for instructions and data, as
139 instructions with the sequence (as described in, e.g., POWER9 Processor
202 v2.07 crypto instructions are available.
214 quad-precision instructions and data types.
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| D | cpu_features.rst | 31 selection, unused code is replaced by 'nop' instructions. This nop'ing is
49 instructions are replaced with nop's.
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| /Documentation/arch/x86/ |
| D | tlb.rst | 15 time. This could potentially cost many more instructions, but
31 instructions have separate TLBs, as do different page sizes.
42 invlpg instruction (or instructions _near_ it) show up high in
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| /Documentation/core-api/ |
| D | asm-annotations.rst | 96 ``.text``. Data do not contain instructions, so they have to be treated
97 specially by the tools: they should not treat the bytes as instructions,
120 the sequence of instructions as a function and computes its size to the
125 example, having some asm instructions in between the macros, of course::
143 result, except the debug information for the instructions is generated to
181 Similar to instructions, there is a couple of macros to describe data in the
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| D | refcount-vs-atomic.rst | 36 each ``atomic_*()`` and ``refcount_*()`` operation is atomic and instructions
42 stores (all po-earlier instructions) on the same CPU are completed
50 stores (all po-earlier instructions) on the same CPU are completed
58 stores (all po-later instructions) on the same CPU are
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| /Documentation/admin-guide/hw-vuln/ |
| D | special-register-buffer-data-sampling.rst | 13 When RDRAND, RDSEED and EGETKEY instructions are used, the data is moved
65 EGETKEY instructions to overwrite secret special register data in the shared
69 During execution of the RDRAND, RDSEED, or EGETKEY instructions, off-core
76 #. RDRAND, RDSEED, or EGETKEY instructions have higher latency.
87 the mitigation for RDRAND and RDSEED instructions executed outside of Intel
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| D | cross-thread-rsb.rst | 62 instructions with targeted return locations and then transitioning out of C0
70 targets by performing a sequence of CALL instructions.
73 intercepting HLT and MWAIT instructions.
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| /Documentation/staging/ |
| D | lzo.rst | 20 The stream is composed of a series of instructions, operands, and data. The
21 instructions consist in a few bits representing an opcode, and bits forming
29 as a piece of information for next instructions.
55 ranges, resulting in multiple copy instructions using different encodings.
74 In the code some length checks are missing because certain instructions
76 because it has already been guaranteed before parsing the instructions.
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| /Documentation/arch/loongarch/ |
| D | introduction.rst | 206 LoongArch instructions are 32 bits wide, belonging to 9 basic instruction
229 List of Instructions
236 1. Arithmetic Instructions::
246 2. Bit-shift Instructions::
251 3. Bit-manipulation Instructions::
258 4. Branch Instructions::
262 5. Load/Store Instructions::
269 6. Atomic Operation Instructions::
275 7. Barrier Instructions::
279 8. Special Instructions::
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| /Documentation/filesystems/ |
| D | ecryptfs.rst | 9 building and installation instructions please see the INSTALL file.
65 Then umount /mnt/crypt and mount again per the instructions given
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| /Documentation/translations/zh_CN/ |
| D | glossary.rst | 26 * MIPS: 每秒百万指令。（Millions of Instructions Per Second）,注意与mips指令集区分开。
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