| /Documentation/devicetree/bindings/interrupt-controller/ |
| D | ingenic,intc.yaml | 4 $id: http://devicetree.org/schemas/interrupt-controller/ingenic,intc.yaml#
19 - ingenic,jz4740-intc
20 - ingenic,jz4760-intc
21 - ingenic,jz4780-intc
24 - ingenic,jz4775-intc
25 - ingenic,jz4770-intc
26 - ingenic,jz4760b-intc
27 - const: ingenic,jz4760-intc
29 - const: ingenic,x1000-intc
30 - const: ingenic,jz4780-intc
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| D | mrvl,intc.yaml | 4 $id: http://devicetree.org/schemas/interrupt-controller/mrvl,intc.yaml#
19 const: marvell,orion-intc
22 - mrvl,intc-nr-irqs
28 - mrvl,mmp-intc
29 - mrvl,mmp2-intc
39 - marvell,mmp3-intc
40 - mrvl,mmp2-mux-intc
49 const: mrvl,mmp2-mux-intc
70 - mrvl,mmp-intc
71 - mrvl,mmp2-intc
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| D | amlogic,meson-gpio-intc.yaml | 4 $id: http://devicetree.org/schemas/interrupt-controller/amlogic,meson-gpio-intc.yaml#
26 - const: amlogic,meson-gpio-intc
29 - amlogic,meson8-gpio-intc
30 - amlogic,meson8b-gpio-intc
31 - amlogic,meson-gxbb-gpio-intc
32 - amlogic,meson-gxl-gpio-intc
33 - amlogic,meson-axg-gpio-intc
34 - amlogic,meson-g12a-gpio-intc
35 - amlogic,meson-sm1-gpio-intc
36 - amlogic,meson-a1-gpio-intc
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| D | ti,omap-intc-irq.txt | 1 Omap2/3 intc controller
3 On TI omap2 and 3 the intc interrupt controller can provide
8 "ti,omap2-intc"
9 "ti,omap3-intc"
10 "ti,dm814-intc"
11 "ti,dm816-intc"
12 "ti,am33xx-intc"
16 source, should be 1 for intc
23 intc: interrupt-controller@48200000 {
24 compatible = "ti,omap3-intc";
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| D | csky,apb-intc.txt | 8 - csky,apb-intc is used in a lot of csky fpgas and socs, it support 64 irq nums.
9 - csky,dual-apb-intc consists of 2 apb-intc and 128 irq nums supported.
10 - csky,gx6605s-intc is gx6605s soc internal irq interrupt controller, 64 irq nums.
13 intc node bindings definition
23 Definition: must be "csky,apb-intc"
24 "csky,dual-apb-intc"
25 "csky,gx6605s-intc"
43 intc: interrupt-controller@500000 {
44 compatible = "csky,apb-intc";
50 intc: interrupt-controller@500000 {
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| D | renesas,irqc.yaml | 27 - renesas,intc-ex-r8a774a1 # RZ/G2M
28 - renesas,intc-ex-r8a774b1 # RZ/G2N
29 - renesas,intc-ex-r8a774c0 # RZ/G2E
30 - renesas,intc-ex-r8a774e1 # RZ/G2H
31 - renesas,intc-ex-r8a7795 # R-Car H3
32 - renesas,intc-ex-r8a7796 # R-Car M3-W
33 - renesas,intc-ex-r8a77961 # R-Car M3-W+
34 - renesas,intc-ex-r8a77965 # R-Car M3-N
35 - renesas,intc-ex-r8a77970 # R-Car V3M
36 - renesas,intc-ex-r8a77980 # R-Car V3H
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| D | brcm,l2-intc.yaml | 4 $id: http://devicetree.org/schemas/interrupt-controller/brcm,l2-intc.yaml#
20 - brcm,hif-spi-l2-intc
21 - brcm,upg-aux-aon-l2-intc
22 - const: brcm,l2-intc
25 - brcm,bcm2711-l2-intc
26 - const: brcm,l2-intc
28 - const: brcm,bcm7271-l2-intc
30 - const: brcm,l2-intc
66 compatible = "brcm,l2-intc";
70 interrupt-parent = <&intc>;
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| D | allwinner,sun6i-a31-r-intc.yaml | 4 $id: http://devicetree.org/schemas/interrupt-controller/allwinner,sun6i-a31-r-intc.yaml#
26 - const: allwinner,sun6i-a31-r-intc
29 - allwinner,sun8i-a83t-r-intc
30 - allwinner,sun8i-h3-r-intc
31 - allwinner,sun50i-a64-r-intc
32 - const: allwinner,sun6i-a31-r-intc
33 - const: allwinner,sun50i-h6-r-intc
59 compatible = "allwinner,sun50i-a64-r-intc",
60 "allwinner,sun6i-a31-r-intc";
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| D | qca,ath79-misc-intc.txt | 7 - compatible: has to be "qca,<soctype>-cpu-intc", "qca,ar7100-misc-intc" or
8 "qca,<soctype>-cpu-intc", "qca,ar7240-misc-intc"
24 compatible = "qca,ar9132-misc-intc", "qca,ar7100-misc-intc";
37 compatible = "qca,ar9331-misc-intc", qca,ar7240-misc-intc";
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| D | renesas,intc-irqpin.yaml | 4 $id: http://devicetree.org/schemas/interrupt-controller/renesas,intc-irqpin.yaml#
7 title: Renesas Interrupt Controller (INTC) for external pins
16 - renesas,intc-irqpin-r8a7740 # R-Mobile A1
17 - renesas,intc-irqpin-r8a7778 # R-Car M1A
18 - renesas,intc-irqpin-r8a7779 # R-Car H1
19 - renesas,intc-irqpin-sh73a0 # SH-Mobile AG5
20 - const: renesas,intc-irqpin
73 - renesas,intc-irqpin-r8a7740
74 - renesas,intc-irqpin-sh73a0
89 compatible = "renesas,intc-irqpin-r8a7740", "renesas,intc-irqpin";
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| D | ti,omap2-intc.txt | 9 "ti,omap2-intc"
15 - ti,intc-size: Number of interrupts handled by the interrupt controller.
16 - reg: physical base address and size of the intc registers map.
20 intc: interrupt-controller@1 {
21 compatible = "ti,omap2-intc";
24 ti,intc-size = <96>;
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| D | ti,cp-intc.txt | 10 "ti,cp-intc"
16 - ti,intc-size: Number of interrupts handled by the interrupt controller.
17 - reg: physical base address and size of the intc registers map.
21 intc: interrupt-controller@1 {
22 compatible = "ti,cp-intc";
25 ti,intc-size = <101>;
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| D | realtek,rtl-intc.yaml | 4 $id: http://devicetree.org/schemas/interrupt-controller/realtek,rtl-intc.yaml#
27 - realtek,rtl8380-intc
28 - realtek,rtl9300-intc
29 - const: realtek,rtl-intc
30 - const: realtek,rtl-intc
67 const: realtek,rtl-intc
82 const: realtek,rtl9300-intc
98 compatible = "realtek,rtl8380-intc", "realtek,rtl-intc";
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| D | snps,arc700-intc.txt | 8 - compatible: "snps,arc700-intc"
15 intc accessed via the special ARC AUX register interface, hence "reg" property
20 intc: interrupt-controller {
21 compatible = "snps,arc700-intc";
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| D | snps,archs-intc.txt | 5 - compatible: "snps,archs-intc"
12 intc accessed via the special ARC AUX register interface, hence "reg" property
17 intc: interrupt-controller {
18 compatible = "snps,archs-intc";
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| D | qca,ath79-cpu-intc.txt | 9 - compatible: has to be "qca,<soctype>-cpu-intc", "qca,ar7100-cpu-intc"
13 source, should be 1 for intc
29 compatible = "qca,ar9132-cpu-intc", "qca,ar7100-cpu-intc";
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| D | marvell,orion-intc.txt | 6 - compatible: shall be "marvell,orion-intc"
18 intc: interrupt-controller {
19 compatible = "marvell,orion-intc";
29 - compatible: shall be "marvell,orion-bridge-intc"
41 compatible = "marvell,orion-bridge-intc";
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| D | rda,8810pl-intc.yaml | 4 $id: http://devicetree.org/schemas/interrupt-controller/rda,8810pl-intc.yaml#
17 const: rda,8810pl-intc
37 intc: interrupt-controller@0 {
38 compatible = "rda,8810pl-intc";
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| D | ti,pruss-intc.yaml | 4 $id: http://devicetree.org/schemas/interrupt-controller/ti,pruss-intc.yaml#
24 defined, it implies that all the PRUSS INTC output interrupts 2 through 9
41 - ti,pruss-intc
42 - ti,icssg-intc
44 Use "ti,pruss-intc" for OMAP-L13x/AM18x/DA850 SoCs,
49 Use "ti,icssg-intc" for K3 AM65x, J721E and AM64x family of SoCs
88 Bitmask of host interrupts between 0 and 7 (corresponding to PRUSS INTC
122 compatible = "ti,pruss-intc";
146 compatible = "ti,pruss-intc";
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| D | cirrus,clps711x-intc.txt | 5 - compatible: Should be "cirrus,ep7209-intc".
36 intc: interrupt-controller {
37 compatible = "cirrus,ep7312-intc", "cirrus,ep7209-intc";
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| D | via,vt8500-intc.txt | 5 - compatible : "via,vt8500-intc"
11 intc: interrupt-controller@d8140000 {
12 compatible = "via,vt8500-intc";
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| D | snps,archs-idu-intc.txt | 5 intc.
9 - compatible: "snps,archs-idu-intc"
31 compatible = "snps,archs-intc";
37 compatible = "snps,archs-idu-intc";
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| D | mstar,mst-intc.yaml | 4 $id: http://devicetree.org/schemas/interrupt-controller/mstar,mst-intc.yaml#
21 const: mstar,mst-intc
42 mstar,intc-no-eoi:
57 compatible = "mstar,mst-intc";
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| D | sunplus,sp7021-intc.yaml | 5 $id: http://devicetree.org/schemas/interrupt-controller/sunplus,sp7021-intc.yaml#
16 - const: sunplus,sp7021-intc
52 intc: interrupt-controller@9c000780 {
53 compatible = "sunplus,sp7021-intc";
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| D | riscv,cpu-intc.yaml | 4 $id: http://devicetree.org/schemas/interrupt-controller/riscv,cpu-intc.yaml#
41 - const: andestech,cpu-intc
42 - const: riscv,cpu-intc
43 - const: riscv,cpu-intc
71 compatible = "riscv,cpu-intc";
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