Searched +full:integratorcp +full:- +full:cm +full:- +full:core (Results 1 – 1 of 1) sorted by relevance
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)3 ---4 $id: http://devicetree.org/schemas/clock/arm,syscon-icst.yaml#5 $schema: http://devicetree.org/meta-schemas/core.yaml#10 - Linus Walleij <linusw@kernel.org>25 connects the low 8 bits of the VDW (missing one bit), hard-wires RDW to26 different values and sometimes also hard-wires the output divider. They30 In the core modules and logic tiles, the ICST is a configurable clock fed32 generating e.g. video clocks. It is located on the core module and there is33 only one of these. This clock node must be a subnode of the core module.[all …]