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/Documentation/devicetree/bindings/interconnect/
Dinterconnect.txt1 Interconnect Provider Device Tree Bindings
4 The purpose of this document is to define a common set of generic interconnect
8 = interconnect providers =
10 The interconnect provider binding is intended to represent the interconnect
11 controllers in the system. Each provider registers a set of interconnect
12 nodes, which expose the interconnect related capabilities of the interconnect
14 etc. The consumer drivers set constraints on interconnect path (or endpoints)
15 depending on the use case. Interconnect providers can also be interconnect
20 - compatible : contains the interconnect provider compatible string
21 - #interconnect-cells : number of cells in a interconnect specifier needed to
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Dqcom,qcm2290.yaml4 $id: http://devicetree.org/schemas/interconnect/qcom,qcm2290.yaml#
7 title: Qualcomm QCM2290 Network-On-Chip interconnect
13 The Qualcomm QCM2290 interconnect providers support adjusting the
31 '^interconnect-[a-z0-9]+$':
34 The interconnect providers do not have a separate QoS register space,
62 snoc: interconnect@1880000 {
65 #interconnect-cells = <1>;
67 qup_virt: interconnect-qup {
69 #interconnect-cells = <1>;
72 mmnrt_virt: interconnect-mmnrt {
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Dqcom,msm8953.yaml4 $id: http://devicetree.org/schemas/interconnect/qcom,msm8953.yaml#
7 title: Qualcomm MSM8953 Network-On-Chip interconnect
13 The Qualcomm MSM8953 interconnect providers support adjusting the
16 See also: include/dt-bindings/interconnect/qcom,msm8953.h
34 '#interconnect-cells':
38 '^interconnect-[a-z0-9\-]+$':
43 The interconnect providers do not have a separate QoS register space,
52 - '#interconnect-cells'
57 - '#interconnect-cells'
89 snoc: interconnect@580000 {
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Dqcom,sm6350-rpmh.yaml4 $id: http://devicetree.org/schemas/interconnect/qcom,sm6350-rpmh.yaml#
7 title: Qualcomm SM6350 RPMh Network-On-Chip Interconnect
13 Qualcomm RPMh-based interconnect provider on SM6350.
33 '#interconnect-cells': true
36 '^interconnect-[a-z0-9\-]+$':
39 The interconnect providers do not have a separate QoS register space,
49 '#interconnect-cells': true
64 config_noc: interconnect@1500000 {
67 #interconnect-cells = <2>;
71 system_noc: interconnect@1620000 {
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Dqcom,sm6115.yaml4 $id: http://devicetree.org/schemas/interconnect/qcom,sm6115.yaml#
7 title: Qualcomm SM6115 Network-On-Chip interconnect
13 The Qualcomm SM6115 interconnect providers support adjusting the
36 '^interconnect-[a-z0-9]+$':
39 The interconnect providers do not have a separate QoS register space,
119 snoc: interconnect@1880000 {
130 #interconnect-cells = <1>;
132 qup_virt: interconnect-clk {
134 #interconnect-cells = <1>;
137 mmnrt_virt: interconnect-mmnrt {
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Dqcom,sm7150-rpmh.yaml4 $id: http://devicetree.org/schemas/interconnect/qcom,sm7150-rpmh.yaml#
7 title: Qualcomm RPMh Network-On-Chip Interconnect on SM7150
13 RPMh interconnect providers support system bandwidth requirements through
16 See also:: include/dt-bindings/interconnect/qcom,sm7150-rpmh.h
39 '^interconnect-[0-9]+$':
42 The interconnect providers do not have a separate QoS register space,
66 mc_virt: interconnect@1380000 {
69 #interconnect-cells = <2>;
73 system_noc: interconnect@1620000 {
76 #interconnect-cells = <2>;
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Dqcom,qdu1000-rpmh.yaml4 $id: http://devicetree.org/schemas/interconnect/qcom,qdu1000-rpmh.yaml#
7 title: Qualcomm RPMh Network-On-Chip Interconnect on QDU1000
14 RPMh interconnect providers support system bandwidth requirements through
29 '#interconnect-cells': true
57 #include <dt-bindings/interconnect/qcom,qdu1000-rpmh.h>
59 system_noc: interconnect@1640000 {
62 #interconnect-cells = <2>;
66 clk_virt: interconnect-0 {
68 #interconnect-cells = <2>;
Dqcom,msm8939.yaml4 $id: http://devicetree.org/schemas/interconnect/qcom,msm8939.yaml#
7 title: Qualcomm MSM8937/MSM8939/MSM8976 Network-On-Chip interconnect
13 The Qualcomm MSM8937/MSM8939/MSM8976 interconnect providers support
36 '^interconnect-[a-z0-9\-]+$':
40 The interconnect providers do not have a separate QoS register space,
68 snoc: interconnect@580000 {
71 #interconnect-cells = <1>;
73 snoc_mm: interconnect-snoc {
75 #interconnect-cells = <1>;
Dqcom,sc7280-rpmh.yaml4 $id: http://devicetree.org/schemas/interconnect/qcom,sc7280-rpmh.yaml#
7 title: Qualcomm RPMh Network-On-Chip Interconnect on SC7280
14 RPMh interconnect providers support system bandwidth requirements through
17 See also:: include/dt-bindings/interconnect/qcom,sc7280.h
104 interconnect {
106 #interconnect-cells = <2>;
110 interconnect@9100000 {
113 #interconnect-cells = <2>;
117 interconnect@16e0000 {
120 #interconnect-cells = <2>;
Dqcom,msm8974.yaml4 $id: http://devicetree.org/schemas/interconnect/qcom,msm8974.yaml#
7 title: Qualcomm MSM8974 Network-On-Chip Interconnect
13 The Qualcomm MSM8974 interconnect providers support setting system
29 '#interconnect-cells':
45 - '#interconnect-cells'
55 bimc: interconnect@fc380000 {
58 #interconnect-cells = <1>;
Dqcom,sdx75-rpmh.yaml4 $id: http://devicetree.org/schemas/interconnect/qcom,sdx75-rpmh.yaml#
7 title: Qualcomm RPMh Network-On-Chip Interconnect on SDX75
13 RPMh interconnect providers support system bandwidth requirements through
30 '#interconnect-cells': true
80 clk_virt: interconnect-0 {
82 #interconnect-cells = <2>;
87 system_noc: interconnect@1640000 {
90 #interconnect-cells = <2>;
Dqcom,rpm-common.yaml4 $id: http://devicetree.org/schemas/interconnect/qcom,rpm-common.yaml#
7 title: Qualcomm RPMh Network-On-Chip Interconnect
13 RPM interconnect providers support for managing system bandwidth requirements
19 '#interconnect-cells':
26 - '#interconnect-cells'
Dqcom,rpmh-common.yaml4 $id: http://devicetree.org/schemas/interconnect/qcom,rpmh-common.yaml#
7 title: Qualcomm RPMh Network-On-Chip Interconnect
14 RPMh interconnect providers support system bandwidth requirements through
22 '#interconnect-cells':
32 this interconnect to send RPMh commands.
40 - '#interconnect-cells'
Dqcom,osm-l3.yaml4 $id: http://devicetree.org/schemas/interconnect/qcom,osm-l3.yaml#
7 title: Qualcomm Operating State Manager (OSM) L3 Interconnect Provider
14 The OSM L3 interconnect provider aggregates the L3 bandwidth requests
51 '#interconnect-cells':
59 - '#interconnect-cells'
69 osm_l3: interconnect@17d41000 {
76 #interconnect-cells = <1>;
Dqcom,sc8280xp-rpmh.yaml4 $id: http://devicetree.org/schemas/interconnect/qcom,sc8280xp-rpmh.yaml#
7 title: Qualcomm RPMh Network-On-Chip Interconnect on SC8280XP
14 RPMh interconnect providers support system bandwidth requirements through
17 See also:: include/dt-bindings/interconnect/qcom,sc8280xp.h
45 interconnect-0 {
47 #interconnect-cells = <2>;
Dqcom,x1e80100-rpmh.yaml4 $id: http://devicetree.org/schemas/interconnect/qcom,x1e80100-rpmh.yaml#
7 title: Qualcomm RPMh Network-On-Chip Interconnect on X1E80100
14 RPMh interconnect providers support system bandwidth requirements through
21 See also:: include/dt-bindings/interconnect/qcom,x1e80100-rpmh.h
72 clk_virt: interconnect-0 {
74 #interconnect-cells = <2>;
78 aggre1_noc: interconnect@16e0000 {
81 #interconnect-cells = <2>;
Dqcom,sa8775p-rpmh.yaml4 $id: http://devicetree.org/schemas/interconnect/qcom,sa8775p-rpmh.yaml#
7 title: Qualcomm RPMh Network-On-Chip Interconnect on SA8775P
13 RPMh interconnect providers support system bandwidth requirements through
16 See also:: include/dt-bindings/interconnect/qcom,sa8775p.h
46 aggre1_noc: interconnect-aggre1-noc {
48 #interconnect-cells = <2>;
Dqcom,sm8450-rpmh.yaml4 $id: http://devicetree.org/schemas/interconnect/qcom,sm8450-rpmh.yaml#
7 title: Qualcomm RPMh Network-On-Chip Interconnect on SM8450
14 RPMh interconnect providers support system bandwidth requirements through
17 See also:: include/dt-bindings/interconnect/qcom,sm8450.h
109 interconnect-0 {
111 #interconnect-cells = <2>;
115 interconnect@1700000 {
118 #interconnect-cells = <2>;
Dqcom,sdm660.yaml4 $id: http://devicetree.org/schemas/interconnect/qcom,sdm660.yaml#
7 title: Qualcomm SDM660 Network-On-Chip interconnect
13 The Qualcomm SDM660 interconnect providers support adjusting the
88 bimc: interconnect@1008000 {
91 #interconnect-cells = <1>;
94 a2noc: interconnect@1704000 {
97 #interconnect-cells = <1>;
Dqcom,rpm.yaml4 $id: http://devicetree.org/schemas/interconnect/qcom,rpm.yaml#
7 title: Qualcomm RPM Network-On-Chip Interconnect
13 RPM interconnect providers support system bandwidth requirements through
46 bimc: interconnect@400000 {
49 #interconnect-cells = <1>;
Dqcom,msm8996.yaml4 $id: http://devicetree.org/schemas/interconnect/qcom,msm8996.yaml#
7 title: Qualcomm MSM8996 Network-On-Chip interconnect
13 The Qualcomm MSM8996 interconnect providers support adjusting the
109 bimc: interconnect@408000 {
112 #interconnect-cells = <1>;
115 a0noc: interconnect@543000 {
118 #interconnect-cells = <1>;
/Documentation/driver-api/
Dinterconnect.rst4 Generic System Interconnect Subsystem
16 The interconnect bus is hardware with configurable parameters, which can be
18 An example of interconnect buses are the interconnects between various
22 Below is a simplified diagram of a real-world SoC interconnect bus topology.
55 Interconnect provider is the software definition of the interconnect hardware.
56 The interconnect providers on the above diagram are M NoC, S NoC, C NoC, P NoC
59 Interconnect node is the software definition of the interconnect hardware
60 port. Each interconnect provider consists of multiple interconnect nodes,
61 which are connected to other SoC components including other interconnect
63 called an interconnect node, which belongs to the Mem NoC interconnect provider.
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/Documentation/devicetree/bindings/bus/
Dti-sysc.yaml7 title: Texas Instruments interconnect target module
13 Texas Instruments SoCs can have a generic interconnect target module
14 for devices connected to various interconnects such as L3 interconnect
15 using Arteris NoC, and L4 interconnect using Sonics s3220. This module
18 than that it is mostly independent of the interconnect.
20 Each interconnect target module can have one or more devices connected to
21 it. There is a set of control registers for managing the interconnect target
22 module clocks, idle modes and interconnect level resets.
24 The interconnect target module control registers are sprinkled into the
26 the interconnect target module. Typically the register names are REVISION,
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Dbaikal,bt1-axi.yaml16 cores. Traffic arbitration is done by means of DW AXI Interconnect (so
17 called AXI Main Interconnect) routing IO requests from one block to
22 (Errors Handler Block) embedded on top of the DW AXI Interconnect and
36 - description: Synopsys DesignWare AXI Interconnect QoS registers
45 '#interconnect-cells':
57 - description: Main Interconnect uplink reference clock
65 - description: Main Interconnect reset line
93 #interconnect-cells = <1>;
/Documentation/devicetree/bindings/soc/imx/
Dfsl,imx8mm-vpu-blk-ctrl.yaml44 interconnect-names:
91 - description: G1 decoder interconnect
92 - description: G2 decoder interconnect
95 interconnect-names:
136 - description: G1 decoder interconnect
137 - description: G2 decoder interconnect
138 - description: VC8000E encoder interconnect
140 interconnect-names:

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