Searched full:internal (Results 1 – 25 of 993) sorted by relevance
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| /Documentation/driver-api/ |
| D | basics.rst | 8 :internal:
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| D | w1.rst | 7 W1 API internal to the kernel
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37 W1 internal initialization for master devices.
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45 W1 internal initialization for master devices.
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| D | infiniband.rst | 14 :internal:
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| D | input.rst | 8 :internal:
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| D | infrastructure.rst | 8 :internal:
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| /Documentation/driver-api/surface_aggregator/ |
| D | internal-api.rst | 4 Internal API Documentation
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| /Documentation/devicetree/bindings/net/ |
| D | fsl,fman-mdio.yaml | 38 fsl,fman-internal-mdio:
41 Fman has internal MDIO for internal PCS(Physical
43 The settings and programming routines for internal/external
44 MDIO are different. Must be included for internal MDIO.
59 set when reading internal PCS registers. MDIO reads to
60 internal PCS registers may result in having the
63 Software may get false read error when reading internal
64 PCS registers through MDIO. As a workaround, all internal
67 For internal PHY device on internal mdio bus, a PHY node should be created.
69 example of how to define a PHY (Internal PHY has no interrupt line).
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| D | adi,adin.yaml | 19 adi,rx-internal-delay-ps:
22 internal delay (phy-mode is 'rgmii-id' or 'rgmii-rxid') in pico-seconds.
26 adi,tx-internal-delay-ps:
29 internal delay (phy-mode is 'rgmii-id' or 'rgmii-txid') in pico-seconds.
44 the 125MHz clocks based on its internal state.
68 adi,rx-internal-delay-ps = <1800>;
69 adi,tx-internal-delay-ps = <2200>;
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| D | ti,dp83822.yaml | 51 rx-internal-delay-ps:
54 Setting this property to a non-zero number sets the RX internal delay
55 for the PHY. The internal delay for the PHY is fixed to 3.5ns relative
58 tx-internal-delay-ps:
61 Setting this property to a non-zero number sets the TX internal delay
62 for the PHY. The internal delay for the PHY is fixed to 3.5ns relative
111 rx-internal-delay-ps = <1>;
112 tx-internal-delay-ps = <1>;
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| D | qcom-emac.txt | 4 internal PHY. Each device is represented by a device tree node. A phandle
5 connects the MAC node to its corresponding internal phy node. Another
16 - internal-phy : phandle to the internal PHY node
19 Internal PHY node:
46 internal-phy = <&emac_sgmii>;
95 internal-phy = <&emac_sgmii>;
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| D | amlogic,meson-dwmac.yaml | 48 - description: First parent clock of the internal mux
49 - description: Second parent clock of the internal mux
64 The internal RGMII TX clock delay (provided by this driver)
81 The internal RGMII RX clock delay in nanoseconds. Deprecated, use
82 rx-internal-delay-ps instead.
84 rx-internal-delay-ps:
98 rx-internal-delay-ps:
111 rx-internal-delay-ps:
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| /Documentation/devicetree/bindings/net/dsa/ |
| D | nxp,sja1105.yaml | 38 # Optional container node for the 2 internal MDIO buses of the SJA1110
39 # (one for the internal 100base-T1 PHYs and the other for the single
93 rx-internal-delay-ps:
94 $ref: "#/$defs/internal-delay-ps"
95 tx-internal-delay-ps:
96 $ref: "#/$defs/internal-delay-ps"
103 internal-delay-ps:
157 rx-internal-delay-ps = <0>;
158 tx-internal-delay-ps = <0>;
165 rx-internal-delay-ps = <0>;
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| D | microchip,lan937x.yaml | 55 rx-internal-delay-ps:
58 tx-internal-delay-ps:
98 phy-mode = "internal";
105 phy-mode = "internal";
112 phy-mode = "internal";
119 phy-mode = "internal";
126 tx-internal-delay-ps = <2000>;
127 rx-internal-delay-ps = <2000>;
140 tx-internal-delay-ps = <2000>;
141 rx-internal-delay-ps = <2000>;
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| D | vitesse,vsc73xx.yaml | 69 rx-internal-delay-ps:
70 $ref: "#/$defs/internal-delay-ps"
71 tx-internal-delay-ps:
72 $ref: "#/$defs/internal-delay-ps"
90 internal-delay-ps:
139 rx-internal-delay-ps = <0>;
140 tx-internal-delay-ps = <0>;
183 rx-internal-delay-ps = <0>;
184 tx-internal-delay-ps = <0>;
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| D | qca8k.yaml | 14 describing a port needs to have a valid phandle referencing the internal PHY
16 ID. To declare the internal mdio-bus configuration, declare an MDIO node in
17 the switch node and declare the phandle for the port, referencing the internal
18 PHY it is connected to. In this config, an internal mdio-bus is registered and
19 the MDIO master is used for communication. Mixed external and internal
65 description: Qca8k switch have an internal mdio to access switch port.
67 internal mdio access is used.
68 With the legacy mapping the reg corresponding to the internal
231 phy-mode = "internal";
257 phy-mode = "internal";
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| /Documentation/devicetree/bindings/sound/ |
| D | img,pistachio-internal-dac.txt | 1 Pistachio internal DAC DT bindings
5 - compatible: "img,pistachio-internal-dac"
8 node which contains the internal dac control registers
14 internal_dac: internal-dac {
15 compatible = "img,pistachio-internal-dac";
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| D | nvidia,tegra-audio-rt5677.yaml | 37 - Internal Mic 1
38 - Internal Mic 2
84 "DMIC L1", "Internal Mic 1",
85 "DMIC R1", "Internal Mic 1",
86 "DMIC L2", "Internal Mic 2",
87 "DMIC R2", "Internal Mic 2",
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| D | mvebu-audio.txt | 24 The first one is mandatory and defines the internal clock.
28 "internal" for the internal clock
45 clock-names = "internal";
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| /Documentation/networking/ |
| D | tipc.rst | 131 :internal:
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| D | kapi.rst | 12 :internal:
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| /Documentation/devicetree/bindings/interrupt-controller/ |
| D | cdns,xtensa-pic.txt | 8 When it's 1, the first cell is the internal IRQ number.
10 specifies whether it's internal (0) or external (1).
12 core variants it may be mapped to different internal IRQ.
19 /* one cell: internal irq number,
20 * two cells: second cell == 0: internal irq number
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| /Documentation/core-api/ |
| D | kernel-api.rst | 10 :internal:
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| /Documentation/gpu/xe/ |
| D | xe_rtp.rst | 10 Internal API
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| /Documentation/devicetree/bindings/clock/ |
| D | mvebu-core-clock.txt | 8 0 = tclk (Internal Bus clock)
15 0 = tclk (Internal Bus clock)
21 0 = tclk (Internal Bus clock)
27 0 = tclk (Internal Bus clock)
30 3 = hclk (SDRAM Controller Internal Clock)
35 0 = tclk (Internal Bus clock)
41 0 = tclk (Internal Bus clock)
47 0 = tclk (Internal Bus clock)
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| /Documentation/admin-guide/ |
| D | rapidio.rst | 46 :internal:
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