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/Documentation/devicetree/bindings/interrupt-controller/
Dsnps,dw-apb-ictl.txt1 Synopsys DesignWare APB interrupt controller (dw_apb_ictl)
3 Synopsys DesignWare provides interrupt controller IP for APB known as
4 dw_apb_ictl. The IP is used as secondary interrupt controller in some SoCs with
5 APB bus, e.g. Marvell Armada 1500. It can also be used as primary interrupt
6 controller in some SoCs, e.g. Hisilicon SD5203.
9 - compatible: shall be "snps,dw-apb-ictl"
10 - reg: physical base address of the controller and length of memory mapped
12 - interrupt-controller: identifies the node as an interrupt controller
13 - #interrupt-cells: number of cells to encode an interrupt-specifier, shall be 1
15 Additional required property when it's used as secondary interrupt controller:
[all …]
Dmarvell,orion-intc.txt1 Marvell Orion SoC interrupt controllers
3 * Main interrupt controller
6 - compatible: shall be "marvell,orion-intc"
7 - reg: base address(es) of interrupt registers starting with CAUSE register
8 - interrupt-controller: identifies the node as an interrupt controller
9 - #interrupt-cells: number of cells to encode an interrupt source, shall be 1
11 The interrupt sources map to the corresponding bits in the interrupt
13 - 0 maps to bit 0 of first base address,
14 - 1 maps to bit 1 of first base address,
15 - 32 maps to bit 0 of second base address, and so on.
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Dsamsung,exynos4210-combiner.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/samsung,exynos4210-combiner.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Samsung Exynos SoC Interrupt Combiner Controller
10 - Krzysztof Kozlowski <krzk@kernel.org>
13 Samsung's Exynos4 architecture includes a interrupt combiner controller which
14 can combine interrupt sources as a group and provide a single interrupt
15 request for the group. The interrupt request from each group are connected to
16 a parent interrupt controller, such as GIC in case of Exynos4210.
[all …]
Dmarvell,mpic.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/marvell,mpic.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Marvell Armada 370, 375, 38x, 39x, XP Interrupt Controller
10 - Marek Behún <kabel@kernel.org>
13 The top-level interrupt controller on Marvell Armada 370 and XP. On these
14 platforms it also provides inter-processor interrupts.
16 On Marvell Armada 375, 38x and 39x this controller is wired under ARM GIC.
26 - description: main registers
[all …]
Dabilis,tb10x-ictl.txt1 TB10x Top Level Interrupt Controller
4 The Abilis TB10x SOC contains a custom interrupt controller. It performs
5 one-to-one mapping of external interrupt sources to CPU interrupts and
9 -------------------
11 - compatible: Should be "abilis,tb10x-ictl"
12 - reg: specifies physical base address and size of register range.
13 - interrupt-congroller: Identifies the node as an interrupt controller.
14 - #interrupt cells: Specifies the number of cells used to encode an interrupt
15 source connected to this controller. The value shall be 2.
16 - interrupts: Specifies the list of interrupt lines which are handled by
[all …]
Dloongson,cpu-interrupt-controller.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/loongson,cpu-interrupt-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: LoongArch CPU Interrupt Controller
10 - Liu Peibao <liupeibao@loongson.cn>
14 const: loongson,cpu-interrupt-controller
16 '#interrupt-cells':
19 interrupt-controller: true
24 - compatible
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Dfaraday,ftintc010.txt1 * Faraday Technologt FTINTC010 interrupt controller
3 This interrupt controller is a stock IP block from Faraday Technology found
7 - compatible: must be one of
9 "cortina,gemini-interrupt-controller" (deprecated)
10 - reg: The register bank for the interrupt controller.
11 - interrupt-controller: Identifies the node as an interrupt controller
12 - #interrupt-cells: The number of cells to define the interrupts.
13 Must be 2 as the controller can specify level or rising edge
16 interrupt-controller/interrupts.txt
20 interrupt-controller@48000000 {
[all …]
Dmti,cpu-interrupt-controller.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/mti,cpu-interrupt-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: MIPS CPU Interrupt Controller
11 IRQs from a devicetree file and create a irq_domain for IRQ controller.
14 platforms internal interrupt controller cascade.
17 - Thomas Bogendoerfer <tsbogend@alpha.franken.de>
21 const: mti,cpu-interrupt-controller
23 '#interrupt-cells':
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Dbrcm,bcm7120-l2-intc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/brcm,bcm7120-l2-intc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Broadcom BCM7120-style Level 2 and Broadcom BCM3380 Level 1 / Level 2
10 - Florian Fainelli <f.fainelli@gmail.com>
13 This interrupt controller hardware is a second level interrupt controller that
14 is hooked to a parent interrupt controller: e.g: ARM GIC for ARM-based
17 Such an interrupt controller has the following hardware design:
19 - outputs multiple interrupts signals towards its interrupt controller parent
[all …]
Dqca,ath79-misc-intc.txt1 Binding for Qualcomm Atheros AR7xxx/AR9XXX MISC interrupt controller
3 The MISC interrupt controller is a secondary controller for lower priority
4 interrupt.
7 - compatible: has to be "qca,<soctype>-cpu-intc", "qca,ar7100-misc-intc" or
8 "qca,<soctype>-cpu-intc", "qca,ar7240-misc-intc"
9 - reg: Base address and size of the controllers memory area
10 - interrupts: Interrupt specifier for the controllers interrupt.
11 - interrupt-controller : Identifies the node as an interrupt controller
12 - #interrupt-cells : Specifies the number of cells needed to encode interrupt
19 Interrupt Controllers bindings used by client devices.
[all …]
Dmarvell,armada-8k-pic.txt1 Marvell Armada 7K/8K PIC Interrupt controller
2 ---------------------------------------------
4 This is the Device Tree binding for the PIC, a secondary interrupt
5 controller available on the Marvell Armada 7K/8K ARM64 SoCs, and
6 typically connected to the GIC as the primary interrupt controller.
9 - compatible: should be "marvell,armada-8k-pic"
10 - interrupt-controller: identifies the node as an interrupt controller
11 - #interrupt-cells: the number of cells to define interrupts on this
12 controller. Should be 1
13 - reg: the register area for the PIC interrupt controller
[all …]
Dmarvell,sei.txt1 Marvell SEI (System Error Interrupt) Controller
2 -----------------------------------------------
4 Marvell SEI (System Error Interrupt) controller is an interrupt
6 them to a single interrupt line (an SPI) on the parent interrupt
7 controller.
9 This interrupt controller can handle up to 64 SEIs, a set comes from the
15 - compatible: should be one of:
16 * "marvell,ap806-sei"
17 - reg: SEI registers location and length.
18 - interrupts: identifies the parent IRQ that will be triggered.
[all …]
Dmarvell,icu.txt1 Marvell ICU Interrupt Controller
2 --------------------------------
4 The Marvell ICU (Interrupt Consolidation Unit) controller is
5 responsible for collecting all wired-interrupt sources in the CP and
6 communicating them to the GIC in the AP, the unit translates interrupt
13 - compatible: Should be "marvell,cp110-icu"
15 - reg: Should contain ICU registers location and length.
17 Subnodes: Each group of interrupt is declared as a subnode of the ICU,
22 - compatible: Should be one of:
23 * "marvell,cp110-icu-nsr"
[all …]
Dnxp,lpc3220-mic.txt1 * NXP LPC32xx MIC, SIC1 and SIC2 Interrupt Controllers
4 - compatible: "nxp,lpc3220-mic" or "nxp,lpc3220-sic".
5 - reg: should contain IC registers location and length.
6 - interrupt-controller: identifies the node as an interrupt controller.
7 - #interrupt-cells: the number of cells to define an interrupt, should be 2.
10 IRQ_TYPE_EDGE_RISING = low-to-high edge triggered,
11 IRQ_TYPE_EDGE_FALLING = high-to-low edge triggered,
12 IRQ_TYPE_LEVEL_HIGH = active high level-sensitive,
13 IRQ_TYPE_LEVEL_LOW = active low level-sensitive.
17 - interrupts: empty for MIC interrupt controller, cascaded MIC
[all …]
Dsnps,archs-idu-intc.txt1 * ARC-HS Interrupt Distribution Unit
3 This optional 2nd level interrupt controller can be used in SMP configurations
9 - compatible: "snps,archs-idu-intc"
10 - interrupt-controller: This is an interrupt controller.
11 - #interrupt-cells: Must be <1> or <2>.
14 Number N of the particular interrupt line of IDU corresponds to the line N+24
15 of the core interrupt controller.
18 - bits[3:0] trigger type and level flags
19 1 = low-to-high edge triggered
20 2 = NOT SUPPORTED (high-to-low edge triggered)
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Dinterrupts.txt1 Specifying interrupt information for devices
4 1) Interrupt client nodes
5 -------------------------
8 "interrupts" property, an "interrupts-extended" property, or both. If both are
11 properties contain a list of interrupt specifiers, one per output interrupt. The
12 format of the interrupt specifier is determined by the interrupt controller to
16 interrupt-parent = <&intc1>;
19 The "interrupt-parent" property is used to specify the controller to which
20 interrupts are routed and contains a single phandle referring to the interrupt
21 controller node. This property is inherited, so it may be specified in an
[all …]
Dstarfive,jh8100-intc.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/starfive,jh8100-intc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: StarFive External Interrupt Controller
10 StarFive SoC JH8100 contain a external interrupt controller. It can be used
11 to handle high-level input interrupt signals. It also send the output
12 interrupt signal to RISC-V PLIC.
15 - Changhuang Liang <changhuang.liang@starfivetech.com>
19 const: starfive,jh8100-intc
[all …]
Dmti,gic.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/mti,gic.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: MIPS Global Interrupt Controller
10 - Paul Burton <paulburton@kernel.org>
11 - Thomas Bogendoerfer <tsbogend@alpha.franken.de>
15 It also supports local (per-processor) interrupts and software-generated
16 interrupts which can be used as IPIs. The GIC also includes a free-running
17 global timer, per-CPU count/compare timers, and a watchdog.
[all …]
Dintel,ixp4xx-interrupt.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/interrupt-controller/intel,ixp4xx-interrupt.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Intel IXP4xx XScale Networking Processors Interrupt Controller
11 - Linus Walleij <linus.walleij@linaro.org>
14 This interrupt controller is found in the Intel IXP4xx processors.
19 The distinct IXP4xx families with different interrupt controller
27 - enum:
28 - intel,ixp42x-interrupt
[all …]
Dcsky,apb-intc.txt2 C-SKY APB Interrupt Controller
5 C-SKY APB Interrupt Controller is a simple soc interrupt controller
6 on the apb bus and we only use it as root irq controller.
8 - csky,apb-intc is used in a lot of csky fpgas and socs, it support 64 irq nums.
9 - csky,dual-apb-intc consists of 2 apb-intc and 128 irq nums supported.
10 - csky,gx6605s-intc is gx6605s soc internal irq interrupt controller, 64 irq nums.
16 Description: Describes APB interrupt controller
20 - compatible
23 Definition: must be "csky,apb-intc"
24 "csky,dual-apb-intc"
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Dmicrochip,lan966x-oic.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/microchip,lan966x-oic.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Microchip LAN966x outband interrupt controller
10 - Herve Codina <herve.codina@bootlin.com>
13 - $ref: /schemas/interrupt-controller.yaml#
16 The Microchip LAN966x outband interrupt controller (OIC) maps the internal
17 interrupt sources of the LAN966x device to an external interrupt.
18 When the LAN966x device is used as a PCI device, the external interrupt is
[all …]
Dbrcm,bcm2835-armctrl-ic.txt1 BCM2835 Top-Level ("ARMCTRL") Interrupt Controller
3 The BCM2835 contains a custom top-level interrupt controller, which supports
4 72 interrupt sources using a 2-level register scheme. The interrupt
5 controller, or the HW block containing it, is referred to occasionally
8 The BCM2836 contains the same interrupt controller with the same
9 interrupts, but the per-CPU interrupt controller is the root, and an
10 interrupt there indicates that the ARMCTRL has an interrupt to handle.
14 - compatible : should be "brcm,bcm2835-armctrl-ic" or
15 "brcm,bcm2836-armctrl-ic"
16 - reg : Specifies base physical address and size of the registers.
[all …]
Dbrcm,bcm2836-l1-intc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/brcm,bcm2836-l1-intc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: BCM2836 per-CPU interrupt controller
10 - Stefan Wahren <wahrenst@gmx.net>
11 - Raspberry Pi Kernel Maintenance <kernel-list@raspberrypi.com>
14 The BCM2836 has a per-cpu interrupt controller for the timer, PMU
16 peripheral (GPU) events, which chain to the BCM2835-style interrupt
17 controller.
[all …]
/Documentation/devicetree/bindings/gpio/
D8xxx_gpio.txt3 This is for the non-QE/CPM/GUTs GPIO controllers as found on
6 Every GPIO controller node must have #gpio-cells property defined,
7 this information will be used to translate gpio-specifiers.
11 The GPIO module usually is connected to the SoC's internal interrupt
12 controller, see bindings/interrupt-controller/interrupts.txt (the
13 interrupt client nodes section) for details how to specify this GPIO
14 module's interrupt.
16 The GPIO module may serve as another interrupt controller (cascaded to
17 the SoC's internal interrupt controller). See the interrupt controller
18 nodes section in bindings/interrupt-controller/interrupts.txt for
[all …]
Dgpio-altera.txt1 Altera GPIO controller bindings
4 - compatible:
5 - "altr,pio-1.0"
6 - reg: Physical base address and length of the controller's registers.
7 - #gpio-cells : Should be 2
8 - The first cell is the gpio offset number.
9 - The second cell is reserved and is currently unused.
10 - gpio-controller : Marks the device node as a GPIO controller.
11 - interrupt-controller: Mark the device node as an interrupt controller
12 - #interrupt-cells : Should be 2. The interrupt type is fixed in the hardware.
[all …]

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