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/Documentation/devicetree/bindings/counter/
Dinterrupt-counter.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/counter/interrupt-counter.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Interrupt counter
10 - Oleksij Rempel <o.rempel@pengutronix.de>
13 A generic interrupt counter to measure interrupt frequency. It was developed
17 Interrupts or gpios are required. If both are defined, the interrupt will
22 const: interrupt-counter
31 - compatible
[all …]
Dti-eqep.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/counter/ti-eqep.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - David Lechner <david@lechnology.com>
15 - ti,am3352-eqep
16 - ti,am62-eqep
22 description: The eQEP event interrupt
30 clock-names:
33 power-domains:
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/Documentation/devicetree/bindings/timer/
Dti,keystone-timer.txt3 This document provides bindings for the 64-bit timer in the KeyStone
4 architecture devices. The timer can be configured as a general-purpose 64-bit
5 timer, dual general-purpose 32-bit timers. When configured as dual 32-bit
9 It is global timer is a free running up-counter and can generate interrupt
10 when the counter reaches preset counter values.
17 - compatible : should be "ti,keystone-timer".
18 - reg : specifies base physical address and count of the registers.
19 - interrupts : interrupt generated by the timer.
20 - clocks : the clock feeding the timer clock.
25 compatible = "ti,keystone-timer";
Dti,da830-timer.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/timer/ti,da830-timer.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Kousik Sanagavarapu <five231003@gmail.com>
13 This is a 64-bit timer found on TI's DaVinci architecture devices. The timer
14 can be configured as a general-purpose 64-bit timer, dual general-purpose
15 32-bit timers. When configured as dual 32-bit timers, each half can operate
18 The timer is a free running up-counter and can generate interrupts when the
19 counter reaches preset counter values.
[all …]
Dsamsung,exynos4210-mct.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/timer/samsung,exynos4210-mct.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Krzysztof Kozlowski <krzk@kernel.org>
14 global timer and CPU local timers. The global timer is a 64-bit free running
15 up-counter and can generate 4 interrupts when the counter reaches one of the
16 four preset counter values. The CPU local timers are 32-bit free running
17 down-counters and generate an interrupt when the counter expires. There is
23 - enum:
[all …]
Dnxp,sysctr-timer.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/timer/nxp,sysctr-timer.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NXP System Counter Module(sys_ctr)
10 - Bai Ping <ping.bai@nxp.com>
13 The system counter(sys_ctr) is a programmable system counter
15 etc. it is intended for use in applications where the counter
22 - nxp,imx95-sysctr-timer
23 - nxp,sysctr-timer
[all …]
Dfsl,ftm-timer.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/timer/fsl,ftm-timer.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Animesh Agarwal <animeshagarwal28@gmail.com>
14 const: fsl,ftm-timer
24 contain an entry for each entry in clock-names.
28 clock-names:
30 - const: ftm-evt
31 - const: ftm-src
[all …]
Darm,arch_timer.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Marc Zyngier <marc.zyngier@arm.com>
11 - Mark Rutland <mark.rutland@arm.com>
13 ARM cores may have a per-core architected timer, which provides per-cpu timers,
17 The per-core architected timer is attached to a GIC to deliver its
18 per-processor interrupts via PPIs. The memory mapped timer is attached to a GIC
24 - items:
25 - const: arm,cortex-a15-timer
[all …]
Drenesas,mtu2.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas Multi-Function Timer Pulse Unit 2 (MTU2)
10 - Geert Uytterhoeven <geert+renesas@glider.be>
11 - Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
14 The MTU2 is a multi-purpose, multi-channel timer/counter with configurable clock inputs
17 Channels share hardware resources but their counter and compare match value are
23 - enum:
24 - renesas,mtu2-r7s72100 # RZ/A1H
[all …]
Dnvidia,tegra-timer.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/timer/nvidia,tegra-timer.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Stephen Warren <swarren@nvidia.com>
13 - if:
17 const: nvidia,tegra210-timer
21 # Either a single combined interrupt or up to 14 individual interrupts
27 - if:
31 - items:
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Dimg,pistachio-gptimer.txt1 * Pistachio general-purpose timer based clocksource
4 - compatible: "img,pistachio-gptimer".
5 - reg: Address range of the timer registers.
6 - interrupts: An interrupt for each of the four timers
7 - clocks: Should contain a clock specifier for each entry in clock-names
8 - clock-names: Should contain the following entries:
10 "slow", slow counter clock
11 "fast", fast counter clock
12 - img,cr-periph: Must contain a phandle to the peripheral control
17 compatible = "img,pistachio-gptimer";
[all …]
Dnxp,tpm-timer.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/timer/nxp,tpm-timer.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Dong Aisheng <aisheng.dong@nxp.com>
15 management applications. The counter, compare and capture registers
17 power modes. TPM can support global counter bus where one TPM drives
18 the counter bus for the others, provided bit width is the same.
23 - const: fsl,imx7ulp-tpm
24 - items:
[all …]
Daltr,timer-1.0.txt5 - compatible : should be "altr,timer-1.0"
6 - reg : Specifies base physical address and size of the registers.
7 - interrupts : Should contain the timer interrupt number
8 - clock-frequency : The frequency of the clock that drives the counter, in Hz.
13 compatible = "altr,timer-1.0";
15 interrupt-parent = <&cpu>;
17 clock-frequency = <125000000>;
/Documentation/admin-guide/perf/
Dimx-ddr.rst7 counters is implemented. This is controlled by the CSV modes programmed in counter
10 Selection of the value for each counter is done via the config registers. There
11 is one register for each counter. Counter 0 is special in that it always counts
13 interrupt is raised. If any other counter overflows, it continues counting, and
14 no interrupt is raised.
23 .. code-block:: bash
25 perf stat -a -e imx8_ddr0/cycles/ cmd
26 perf stat -a -e imx8_ddr0/read/,imx8_ddr0/write/ cmd
28 AXI filtering is only used by CSV modes 0x41 (axid-read) and 0x42 (axid-write)
33 un-supported, and value 1 for supported.
[all …]
Dhns3-pmu.rst10 latency, packet rate and interrupt rate.
53 event pair. And the bit 16 of config indicates getting counter 0 or
54 counter 1 of hardware event.
59 counter 0 / counter 1
64 filter mode supported: global/port/port-tc/func/func-queue/
71 ------------------------------------------
73 …$# perf stat -g -e hns3_pmu_sicl_0/bw_ssu_rpu_byte_num,global=1/ -e hns3_pmu_sicl_0/bw_ssu_rpu_tim…
75 …$# perf stat -g -e hns3_pmu_sicl_0/config=0x00002,global=1/ -e hns3_pmu_sicl_0/config=0x10002,glob…
79 --------------
86 $# perf stat -a -e hns3_pmu_sicl_0/config=0x1020F,global=1/ -I 1000
[all …]
/Documentation/devicetree/bindings/arm/
Darm,cci-400.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/arm/arm,cci-400.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
13 ARM multi-cluster systems maintain intra-cluster coherency through a cache
24 pattern: "^cci(@[0-9a-f]+)?$"
28 - arm,cci-400
29 - arm,cci-500
30 - arm,cci-550
[all …]
/Documentation/devicetree/bindings/mfd/
Dst,stm32-lptimer.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mfd/st,stm32-lptimer.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: STMicroelectronics STM32 Low-Power Timers
10 The STM32 Low-Power Timer (LPTIM) is a 16-bit timer that provides several
12 - PWM output (with programmable prescaler, configurable polarity)
13 - Trigger source for STM32 ADC/DAC (LPTIM_OUT)
14 - Several counter modes:
15 - quadrature encoder to detect angular position and direction of rotary
[all …]
Dst,stm32-timers.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mfd/st,stm32-timers.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - advanced-control timers consist of a 16-bit auto-reload counter driven
14 - general-purpose timers consist of a 16-bit or 32-bit auto-reload counter
16 - basic timers consist of a 16-bit auto-reload counter driven by a
20 - Fabrice Gasnier <fabrice.gasnier@foss.st.com>
24 const: st,stm32-timers
32 clock-names:
[all …]
/Documentation/devicetree/bindings/rtc/
Dloongson,rtc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Loongson Real-Time Clock
10 The Loongson family chips use an on-chip counter 0 (Time Of Year
11 counter) as the RTC.
14 - Binbin Zhou <zhoubinbin@loongson.cn>
17 - $ref: rtc.yaml#
22 - enum:
23 - loongson,ls1b-rtc
[all …]
/Documentation/virt/kvm/x86/
Dtimekeeping.rst1 .. SPDX-License-Identifier: GPL-2.0
4 Timekeeping Virtualization for X86-Based Architectures
32 information relevant to KVM and hardware-based virtualization.
41 2.1. i8254 - PIT
42 ----------------
44 One of the first timer devices available is the programmable interrupt timer,
46 channels which can be programmed to deliver periodic or one-shot interrupts.
53 The PIT uses I/O ports 0x40 - 0x43. Access to the 16-bit counters is done
59 -------------- ----------------
61 | 1.1932 MHz|---------->| CLOCK OUT | ---------> IRQ 0
[all …]
/Documentation/timers/
Dhpet.rst8 Each HPET has one fixed-rate counter (at 10+ MHz, hence "High Precision")
13 independent of each other ... these share a counter, complicating resets.
15 HPET devices can support two interrupt routing modes. In one mode, the
16 comparators are additional interrupt sources with no particular system
/Documentation/ABI/testing/
Dsysfs-bus-counter1 What: /sys/bus/counter/devices/counterX/cascade_counts_enable
3 Contact: linux-iio@vger.kernel.org
5 Indicates the cascading of Counts on Counter X.
9 What: /sys/bus/counter/devices/counterX/external_input_phase_clock_select
11 Contact: linux-iio@vger.kernel.org
14 Counter X.
16 MTCLKA-MTCLKB:
20 MTCLKC-MTCLKD:
24 What: /sys/bus/counter/devices/counterX/external_input_phase_clock_select_available
26 Contact: linux-iio@vger.kernel.org
[all …]
/Documentation/devicetree/bindings/perf/
Darm,smmu-v3-pmcg.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/perf/arm,smmu-v3-pmcg.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Arm SMMUv3 Performance Monitor Counter Group
10 - Will Deacon <will@kernel.org>
11 - Robin Murphy <robin.murphy@arm.com>
14 An SMMUv3 may have several Performance Monitor Counter Group (PMCG).
20 pattern: "^pmu@[0-9a-f]*"
23 - items:
[all …]
/Documentation/devicetree/bindings/watchdog/
Dstarfive,jh7100-wdt.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/watchdog/starfive,jh7100-wdt.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Xingyu Wu <xingyu.wu@starfivetech.com>
11 - Samin Guo <samin.guo@starfivetech.com>
16 timeout phases. At the first phase, the signal of watchdog interrupt
17 output(WDOGINT) will rise when counter is 0. The counter will reload
18 the timeout value. And then, if counter decreases to 0 again and WDOGINT
25 - enum:
[all …]
/Documentation/arch/mips/
Dingenic-tcu.rst1 .. SPDX-License-Identifier: GPL-2.0
4 Ingenic JZ47xx SoCs Timer/Counter Unit hardware
7 The Timer/Counter Unit (TCU) in Ingenic JZ47xx SoCs is a multi-function
11 - JZ4725B, JZ4750, JZ4755 only have six TCU channels. The other SoCs all
14 - JZ4725B introduced a separate channel, called Operating System Timer
15 (OST). It is a 32-bit programmable timer. On JZ4760B and above, it is
16 64-bit.
18 - Each one of the TCU channels has its own clock, which can be reparented to three
21 - The watchdog and OST hardware blocks also feature a TCSR register with the same
23 - The TCU registers used to gate/ungate can also gate/ungate the watchdog and
[all …]

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